Searching for "Reducing Test Power" – sorted by Relevance.
27 documents found, showing 1 through 10.
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A Unified Approach to Reduce SOC Test Data Volume, Scan Power and Testing Time
- …, MARCH 2003 A Unified Approach to Reduce SOC Test Data Volume, Scan Power and Testing Time Anshuman…
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On Reducing Both Shift and Capture Power for Scan-Based Testing 1 Key Laboratory of Computer System
- …On Reducing Both Shift and Capture Power for Scan-Based Testing 1 Key Laboratory of Computer…
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Bist power reduction using scan-chain disable in the cell processor
- …’t-care scan chains can be disabled, therefore significantly reducing test power. Index Terms— Microprocessor…
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Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction
- … results show that the proposed technique is very effective in reducing test power. 1 Introduction One…
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SPARTAN: A Spectral and Information Theoretic Approach to Partial-Scan
- … application time (TAT), and reduce test power based [7–11], testability-measure based [12], and test…
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Low Power Pattern Generation for BIST Architecture
- … reduces the switching activities inside the circuit under test, and hence, power consumption. The random…
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On Capture Power-Aware Test Data Compression for Scan-Based Testing ABSTRACT
- … of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we…
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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
- …. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan…
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Low power scan design using first level supply gating
- … for periodic self-test. It is also important to improve test cost, since reduced test power of a module allows…
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iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan
- …-filling techniques have been proposed in literature to reduce shift- and/or capture-power in scan-based testing…
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