Searching for authors named "Ranga Vemuri" – sorted by Relevance.
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Constraints File Format for PDL Verifier
- Constraints File Format for PDL Verifier (.udefs file) Created : October 30, 1995 by Ranga Vemuri
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A Fast Algorithm for Finding Maximal Empty Rectangles For Dynamic FPGA Placement
- Handa and Ranga Vemuri Department of ECECS, University of Cincinnati, Cincinnati, OH 45221-0030, USA
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An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement
- Improvement Satish Ganesan and Ranga Vemuri Department of ECECS, ML 0030 University of Cincinnati
- Cited by 6 (0 self) – Add To MetaCart
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A Power Simulator for VHDL Structural Descriptions
- Conference 1995, pp 4.17-4.25) Srinivas Katkoori and Ranga Vemuri ECE&CS Department University of Cincinnati
- Cited by 1 (0 self) – Add To MetaCart
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Efficient Resource Arbitration in Reconfigurable Computing Environments
- Efficient Resource Arbitration in Reconfigurable Computing Environments Iyad Ouaiss and Ranga
- Cited by 3 (1 self) – Add To MetaCart
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Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs
- -Time Reconfigured Designs Meenakshi Kaul Ranga Vemuri mkaul@(email omitted); Ranga.Vemuri@(email omitted); Laboratory
- Cited by 10 (4 self) – Add To MetaCart
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Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures
- Architectures ? Meenakshi Kaul Ranga Vemuri mkaul@(email omitted); Ranga.Vemuri@(email omitted); Department of ECECS
- Cited by 3 (2 self) – Add To MetaCart
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The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems
- and Ranga Vemuri fadoboli,rangag@(email omitted); Department of ECECS University of Cincinnati Cincinnati, OH
- Cited by 4 (3 self) – Add To MetaCart
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Improving the Schedule Quality of Static-List Time-Constrained Scheduling
- and Ranga Vemuri Digital Design Environments Laboratory, Department of ECECS, ML. 30 University
- Cited by 1 (0 self) – Add To MetaCart
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Cone-Based Clustering Heuristic for List-Scheduling Algorithms
- for Correspondence, (513)-556-4784 (Voice), (513)- 556-7326 (FAX), Ranga.Vemuri@(email omitted); ing the DFG into time steps
- Cited by 8 (3 self) – Add To MetaCart

