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Searching for authors named "Ran Ginosar" – sorted by Relevance.

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33 documents found, showing 1 through 10. Next 10 →

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All-Digital DLL Architecture and Applications
by Tuvia Liran, Ran Ginosar
…All-Digital DLL Architecture and Applications Tuvia Liran 1 and Ran Ginosar 2 1 DFM, Ltd., Kiryat…
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Formal verification of synchronizers
by Tsachy Kapschitz, Ran Ginosar — 2005 — In CHARME 2005
…Formal Verification of Synchronizers Tsachy Kapschitz and Ran Ginosar VLSI Systems Research Center…
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Adaptive Synchronization for Multi-Synchronous Systems
by Rakefet Kol, Ran Ginosar — 1994 — Comput. Methods Appl. Mech. Engrg
…Adaptive Synchronization for Multi-Synchronous Systems Abstract Rakefet Kol and Ran Ginosar…
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BENCHMARKING SPACEWIRE NETWORKS
by Asaf Baron, Ran Ginosar, Isaac Keslassy, Ofer Lapid — 2007 — 1st International SpaceWire Conference
…'har Walter, Ran Ginosar and Isaac Keslassy VLSI Systems Research Center, Elec. Eng. Dept., Technion, Haifa…
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Adaptive Sensitivity
by Ccd Image, Sarit Chen, Ran Ginosar
…Adaptive Sensitivity TM CCD Image Sensor Sarit Chen and Ran Ginosar Department of Electrical…
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Routing table minimization for irregular mesh NoCs
by Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny — 2007 — in Proceedings of Design Automation and Test in Europe (DATE ’07
…Routing Table Minimization for Irregular Mesh NoCs Evgeny Bolotin, Israel Cidon, Ran Ginosar…
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QoS Architecture and Design Process for Cost Effective Networks on Chip
by Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny — 2004 — J. Systems Architecture, special issue on Networks on Chip
… Cidon, Ran Ginosar and Avinoam Kolodny Electrical Engineering Department, Technion—Israel Institute…
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Low-Leakage Repeaters for NoC Interconnects", Special Session "Repeater Insertion for Nanometer Technologies - Timing is NOT Everything
by Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar — 2005 — Proc. of ISCAS
…, Ran Ginosar Electrical Engineering Department, Technion – Israel Institute of Technology, Haifa…
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Self-Timed Architecture Of A Reduced Instruction Set Computer
by Ilana David, Ran Ginosar, Michael Yoeli — 1993 — Asynchronous Design Methodologies
…SELF-TIMED ARCHITECTURE OF A REDUCED INSTRUCTION SET COMPUTER Ilana David 1 , Ran Ginosar 1 ,2…
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Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems
by Rakefet Kol, Ran Ginosar, Goel Samuel — 1996 — In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems (Async96
… Systems Rakefet Kol, Ran Ginosar and Goel Samuel, Nonmembers VLSI Systems Research Center, Electrical…
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