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Searching for authors named "Rajeev Barua" – sorted by Relevance.

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34 documents found, showing 1 through 10. Next 10 →

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EPIC Instruction Scheduling Based on Optimal Approaches
by Steve Haga, Rajeev Barua — 2001 — In Proc. First Annual Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology
…EPIC Instruction Scheduling Based on Optimal Approaches Steve Haga Rajeev Barua Department…
Cited by 10 (0 self) – Add To MetaCart

Compiler Support for Scalable and Efficient Memory Systems
by Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal — 2001
…Compiler Support for Scalable and Efficient Memory Systems Rajeev Barua y , Walter Lee z…
Cited by 11 (1 self) – Add To MetaCart

Dynamic Functional Unit Assignment for Low Power
by Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu — 2003 — in Proc. IEEE Design, Automation and Test in Europe Conf
… & Computer Engineering University of Maryland College Park, MD 20742, U.S.A Rajeev Barua Department…
Cited by 2 (0 self) – Add To MetaCart

Addressing Partitioned Arrays in Distributed Memory Multiprocessors - the Software Virtual Memory Approach
by Rajeev Barua, David Kranz, Anant Agarwal — 1996
… Approach Rajeev Barua David Kranz Anant Agarwal Laboratory for Computer Science Massachusetts Institute…
Cited by 1 (1 self) – Add To MetaCart

Memory Bank Disambiguation using Modulo Unrolling for Raw Machines
by Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal — 1998 — In Proceedings of the ACM/IEEE Fifth Int'l Conference on High Performance Computing(HIPC
…Memory Bank Disambiguation using Modulo Unrolling for Raw Machines Rajeev Barua, Walter Lee, Saman…
Cited by 10 (3 self) – Add To MetaCart

Execution History Guided Instruction Prefetching
by Yi Zhang, Steve Haga, Rajeev Barua — 2002 — in Proc. Intl. Conf. on Supercomputing, 2002
…Execution History Guided Instruction Prefetching Yi Zhang Steve Haga Rajeev Barua Department…
Cited by 6 (0 self) – Add To MetaCart

MTSS: Multi Task Stack Sharing for Embedded Systems
by Bhuvan Middha, Matthew Simpson, Rajeev Barua — 2005 — In Proc. of the Intl. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems (CASES
… physical Author’s address: Rajeev Barua, Dept. of Electrical and Computer Engineering, University…
Cited by 1 (0 self) – Add To MetaCart

Reducing code size in VLIW instruction scheduling
by Steve Haga, Yi Zhang, Andrew Webber, Rajeev Barua — Journal of Embedded Computing
…Reducing Code Size in VLIW Instruction Scheduling Steve Haga, Yi Zhang, Andrew Webber, Rajeev…
Cited by 1 (0 self) – Add To MetaCart

Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors
by Rajeev Barua, David Kranz, Anant Agarwal — 1996 — In Proceedings of the Ninth Workshop on Languages and Compilers for Parallel Computing
…-Coherent Distributed-Memory Multiprocessors Rajeev Barua, David Kranz and Anant Agarwal Laboratory for Computer Science…
Cited by 15 (2 self) – Add To MetaCart

Memory allocation for embedded systems with a compile-time-unknown scratch-pad size
by Nghi Nguyen, Angel Dominguez, Rajeev Barua — 2005 — the ACM Transactions on Embedded Computing Systems (TECS
… Angel Dominguez Rajeev Barua nghi@(email omitted); angelod@(email omitted); barua@(email omitted); ABSTRACT This paper…
Cited by 8 (1 self) – Add To MetaCart

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