Searching for authors named "Priyank Kalla" – sorted by Relevance.
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SIMULATION BOUNDS FOR EQUIVALENCE VERIFICATION OF ARITHMETIC DATAPATHS WITH FINITE WORD-LENGTH OPERANDS ∗
- -LENGTH OPERANDS ∗ Namrata Shekhar, Priyank Kalla Electrical & Computer Engineering Department University
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Enhanced Interior Gateway Routing Protocol, Cisco White Paper
- Durairaj and Priyank Kalla Department of Electrical and Computer Engineering University of Utah, Salt Lake
- Cited by 1 (1 self) – Add To MetaCart
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Dynamic Analysis of Constraint-Variable Dependencies to Guide
- and Priyank Kalla Department of Electrical and Computer Engineering University of Utah, Salt Lake City, UT
- Cited by 1 (1 self) – Add To MetaCart
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A Comprehensive Approach to the Partial Scan Problem Using Implicit State Enumeration
- Identifier S 0278-0070(02)05632-4. Priyank Kalla and Maciej Ciesielski, Senior Member, IEEE 0278
- Cited by 3 (0 self) – Add To MetaCart
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Equivalence Verification of Polynomial Datapaths with Fixed-Size Bit-Vectors using Finite Ring Algebra
- ALGEBRA Namrata Shekhar ∗ , Priyank Kalla ∗ , Florian Enescu † and Sivaram Gopalakrishnan ∗ Abstract
- Cited by 5 (4 self) – Add To MetaCart
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Exploiting vanishing polynomials for equivalence verification of fixed-size arithmetic datapaths
- ∗ Namrata Shekhar 1 , Priyank Kalla 1 , Florian Enescu 2 , Sivaram Gopalakrishnan 1 1 Department
- Cited by 2 (2 self) – Add To MetaCart
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P.: “Integrating CNF and BDD Based SAT Solvers
- Integrating CNF and BDD Based SAT Solvers Sivaram Gopalakrishnan, Vijay Durairaj and Priyank Kalla
- Cited by 1 (0 self) – Add To MetaCart
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Optimization of arithmetic datapaths with finite word-length operands
- , Priyank Kalla 1 and Florian Enescu 2 1 Electrical & Computer Engineering, University of Utah, Salt Lake
- Cited by 1 (1 self) – Add To MetaCart
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BDD-based logic synthesis for LUT-based FPGAs
- , OR and Priyank Kalla University of Utah, Salt Lake City, UT and Russell Tessier University of Massachusetts
- Cited by 7 (1 self) – Add To MetaCart
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Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence
- Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence Priyank
- Cited by 1 (0 self) – Add To MetaCart

