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Searching for "Pipelined Adders." – sorted by Relevance.

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88 documents found, showing 1 through 10. Next 10 →

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Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders
by Mary D. Brown, Yale N. Patt — 2001 — In Proceedings of the 8th Annual International Symposium on High-Performance Computer Architecture
… Pipelined Adders and Register Files Mary D. Brown Yale N. Patt Electrical and Computer Engineering…
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HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS
by unknown authors
… AND ADDERS ABSTRACT In regular FIR structure, by pipelining the multipliers one can improve the throughput…
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High Throughput Pow Er-Aw Are Fir Filter Design Based On Fine-Grain Pipelining Multipliers
by Jia Di Yu
… AND ADDERS ABSTRACT In regular FIR structure, by pipelining the multipliers one can improve the throughput…
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Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications
by Montek Singh, Steven M. Nowick — 2000
…, Florida. Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications £ Abstract A new…
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A Variable Latency Pipelined Floating-Point Adder
by Stuart Oberman And, Stuart F. Oberman, Stuart F. Oberman, Stuart F. Oberman, Michael J. Flynn, Michael J. Flynn, Michael J. Flynn — 1996
…A VARIABLE LATENCY PIPELINED FLOATING-POINT ADDER Stuart F. Oberman and Michael J. Flynn Technical…
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A 14-bit 10MSamples/s D/A Converter Using Multibit - Modulation
by Katayoun Falakshahi, Chih-kong Ken Yang, Bruce A. Wooley — 1999 — IEEE Journal of Solid-State Circuits
…-to-analog conversion, mixed analog–digital integrated circuits, multibit modulators, pipelined adders, sigma…
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RSFQ Arithmetic Blocks for DSP Applications
by Stas Polonsky, Jao Ching Lin, Er V. Rylyakov — 1995
… developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ…
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Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI
by Hamid Mahmoodi-Meimand, Ali Afzali-kusha
… to a 6-stage pipelined adder with two phase clocking. It generates one output each cycle and has a…
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Pipeline Morphing and Virtual Pipelines
by W. Luk, N. Shirazi, S. R. Guo, P. Y. K. Cheung — 1997 — In 7th International Workshop on Field-Programmable Logic and Applications
…-level operators. In the next section, we shall explain how a pipelined adder can be morphed into a pipelined…
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Pipeline Morphing and Virtual Pipelines
by Luk Shirazi Guo, W. Luk, N. Shirazi, S. R. Guo, P. Y. K. Cheung — 1997 — In 7th International Workshop on Field-Programmable Logic and Applications
… also be applied to bit-level operators. In the next section, we shall explain how a pipelined adder can…
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