Searching for authors named "Pierre Michaud" – sorted by Relevance.
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Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration
- Pierre Michaud IRISA/INRIA Campus de Beaulieu 35042 Rennes Cedex, France pmichaud@(email omitted); Abstract We
- Cited by 8 (1 self) – Add To MetaCart
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A PPM-like, tag-based branch predictor
- -like, tag-based branch predictor Pierre Michaud pmichaud@(email omitted); IRISA/INRIA Campus de Beaulieu, Rennes
- Cited by 8 (1 self) – Add To MetaCart
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ATMI 2.0 manual
- ATMI 2.0 manual Pierre Michaud pmichaud@(email omitted); August 17, 2009 • ATMI is an analytical model
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Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
- Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors Pierre Michaud
- Cited by 68 (0 self) – Add To MetaCart
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Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors
- Michaud IRISA/INRIA pmichaud@(email omitted); Andre Seznec Compaq Computer Corporation seznec
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A Statistical Model of Skewed-Associativity
- -associativity is not very efficient when the Pierre Michaud IRISA/INRIA Campus de Beaulieu, 35042 Rennes Cedex, France
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Skewed Branch Predictors
- AUTOMATIQUE Skewed branch predictors Pierre Michaud, Andre Seznec, Richard Uhlig N 2978 Septembre 1996 TH
- Cited by 18 (1 self) – Add To MetaCart
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Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
- Trading Conflict and Capacity Aliasing in Conditional Branch Predictors Pierre Michaud Andre Seznec
- Cited by 75 (6 self) – Add To MetaCart
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Multiple-Block Ahead Branch Predictors
- 1996 Andr'e Seznec y St'ephan Jourdan z Pascal Sainrat z Pierre Michaud y IRISA y IRIT z Campus de
- Cited by 57 (5 self) – Add To MetaCart
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An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors
- Michaud, Andr'e Seznec, St'ephan Jourdan Abstract : The performance of superscalar processors depends
- Cited by 6 (0 self) – Add To MetaCart

