Searching for authors named "Peter Celinski" – sorted by Relevance.
5 documents found, showing 1 through 5.
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Area efficient, high speed parallel counter circuits using charge recycling threshold logic
- …AREA EFFICIENT, HIGH SPEED PARALLEL COUNTER CIRCUITS USING CHARGE RECYCLING THRESHOLD LOGIC Peter…
- Cited by 1 (1 self) – Add To MetaCart
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Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/thresholdlogic approach
- …-CMOS/Threshold-Logic Approach Peter Celinski, Said Al-Sarawi, Derek Abbott Centre for High Performance Integrated Technologies…
- Cited by 2 (0 self) – Add To MetaCart
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Low depth carry lookahead addition using charge recycling threshold logic
- …LOW DEPTH CARRY LOOKAHEAD ADDITION USING CHARGE RECYCLING THRESHOLD LOGIC Peter Celinski, Said Al…
- Cited by 4 (3 self) – Add To MetaCart
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State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications
- …State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications Peter Celinski…
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A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder
- …A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder Peter Celinski 1…
- Cited by 2 (2 self) – Add To MetaCart
Showing 1 through 5.
