Searching for "PROMPT a mapping environment for telecom applications on "system-on-a-chip"." – sorted by Relevance.

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902 documents found, showing 1 through 10. Next 10 →

PROMPT: A Mapping Environment for Telecom Applications on "System-On-a-Chip"
by Michel Barreteau, Juliette Mattioli, Domaine De Corbeville, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Le Chesnay (france, Corinne Ancourt, Franois Irigoin, Rue Saint, Bernard Dion — In CASE2000, Int. Conf. on Compilers, Architecture and Synthesis for Embedded Systems
…PROMPT: A Mapping Environment for Telecom Applications on "System-On-a-Chip" Michel Barreteau…
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System-on-a-chip
by Jump To Navigation
…System-on-a-chip From Wikipedia, the free encyclopedia Jump to: navigation, search System-on-a-chip…
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The System-on-a-Chip Lock Cache
by Bilge Ebru Saglam Akgul — 2004
… technique that is easily applicable to a shared-memory multiprocessor System-on-a-Chip (SoC). Our solution…
Cited by 9 (3 self) – Add To MetaCart

System-on-a-Chip Processor Synchronization
by Support In Hardware — 2001
…System-on-a-Chip Processor Synchronization Support in Hardware Bilge E. Saglam Vincent J. Mooney…
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Embedded Model Predictive Control for System-on-a-Chip Applications
by Leonidas G. Bleris, Mayuresh V. Kothare, Jesus Garcia, Mark G. Arnold — 2004 — Journal of Process Control
…EMBEDDED MODEL PREDICTIVE CONTROL FOR SYSTEM-ON-A-CHIP APPLICATIONS Leonidas G. Bleris…
Cited by 8 (6 self) – Add To MetaCart

Optimal Test Access Architectures for System-on-a-Chip
by Krishnendu Chakrabarty — 2001 — ACM Transactions on Design Automation of Electronic Systems
…Optimal Test Access Architectures for System-on-a-Chip KRISHNENDU CHAKRABARTY Duke University Test…
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SYSTEM-ON-A-CHIP (SOC) VERIFICATION METHODS
by Morgan Chen — 2003
…SYSTEM-ON-A-CHIP (SOC) VERIFICATION METHODS December 6th, 2003 Morgan Chen E-mail: mjchen…
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ERROR CONTAINMENT IN THE TIME- TRIGGERED SYSTEM-ON-A-CHIP ARCHITECTURE
by R. Obermaisser, H. Kopetz, C. El Salloum, B. Huber, R. Obermaisser, H. Kopetz, C. El Salloum, B. Huber
…ERROR CONTAINMENT IN THE TIME- TRIGGERED SYSTEM-ON-A-CHIP ARCHITECTURE R. Obermaisser, H. Kopetz…
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Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test
by Krishnendu Chakrabarty Rajatish, Krishnendu Chakrabarty Y, Rajatish Mukherjee Z, Andrew Exnicios Y — 2001
…Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test 1 Krishnendu…
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System-on-a-Chip - A Platform Perspective
by Jan Rabaey And, Jan M. Rabaey, Alberto Sangiovanni-vincentelli
…Biography System-on-a-Chip - A Platform Perspective Jan M. Rabaey and Alberto Sangiovanni…
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