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Searching for "Of Gates and Wires." – sorted by Relevance.

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418 documents found, showing 1 through 10. Next 10 →

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Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
by Chung-ping Chen, Chris C. N. Chu, D. F. Wong — 1997 — In Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
…Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation Chung-Ping Chen, Chris C…
Cited by 54 (6 self) – Add To MetaCart

Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
by Iris Hui-ru Jiang, Yao-wen Chang, Jing-yang Jou — 2000 — IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems
…, SEPTEMBER 2000 999 Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing Iris Hui…
Cited by 16 (2 self) – Add To MetaCart

Synthesis for multiple input wires replacement of a gate for wiring consideration
by Shih-chieh Chang, Zhong-zhen Wu, Sheng-hong Tu — 1999 — in Int'l Conf. on Computer--Aided Design
…Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications Shih…
Cited by 6 (1 self) – Add To MetaCart

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian
by Hui-ru Jiang, Jing-yang Jou, Yao-wen Chang — 1999 — In Proc. of DAC99, Design Automation Conference
…Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based…
Cited by 5 (3 self) – Add To MetaCart

Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables
by Lizheng Zhang, Student Member, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-ping Chen
… is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations…
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Correlation-Preserved Non-Gaussian Statistical Timing Analysis With Quadratic Timing Model
by Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-ping Chen — 2005
… and more significant. Due to the nonlinearity of the mapping from variation sources to the gate/wire delay…
Cited by 11 (1 self) – Add To MetaCart

A Potentially Implementable FPGA for Quantum Dot Cellular Automata
by Michael Thaddeus Niemier, Arun Francis Rodrigues, Peter M. Kogge — 2002 — Automata”, 1st Workshop on Non-Silicon Computation (NSC-1
… circuit – devices, logic gates, wires, etc. This study introduces the beginning of a next step…
Cited by 8 (0 self) – Add To MetaCart

Defect Tolerance on the Teramac Custom Computer
by W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider — 1997 — in Proceedings of the 1997 IEEE Symposium on FPGA’s for Custom Computing Machines (FCCM ’97
… an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires…
Cited by 23 (0 self) – Add To MetaCart

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
by Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
… application in timing analysis by propagating a waveform along a path containing both gates and wires. When…
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What is the cost of Delay Insensitivity
by Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexander Yakovlev — 1999
… techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit…
Cited by 4 (3 self) – Add To MetaCart

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