Searching for "Of Gates and Wires." – sorted by Relevance.
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Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
- Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation Chung-Ping Chen, Chris C
- Cited by 54 (6 self) – Add To MetaCart
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Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
- , SEPTEMBER 2000 999 Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing Iris Hui
- Cited by 16 (2 self) – Add To MetaCart
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Synthesis for multiple input wires replacement of a gate for wiring consideration
- Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications Shih
- Cited by 6 (1 self) – Add To MetaCart
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Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian
- Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based
- Cited by 5 (3 self) – Add To MetaCart
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Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables
- is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations
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Correlation-Preserved Non-Gaussian Statistical Timing Analysis With Quadratic Timing Model
- and more significant. Due to the nonlinearity of the mapping from variation sources to the gate/wire delay
- Cited by 11 (1 self) – Add To MetaCart
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A Potentially Implementable FPGA for Quantum Dot Cellular Automata
- circuit – devices, logic gates, wires, etc. This study introduces the beginning of a next step
- Cited by 8 (0 self) – Add To MetaCart
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Defect Tolerance on the Teramac Custom Computer
- an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires
- Cited by 23 (0 self) – Add To MetaCart
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Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
- application in timing analysis by propagating a waveform along a path containing both gates and wires. When
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What is the cost of Delay Insensitivity
- techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit
- Cited by 4 (3 self) – Add To MetaCart

