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Searching for authors named "Nicola Nicolici" – sorted by Relevance.

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14 documents found, showing 1 through 10. Next 10 →

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Delay Fault Testing of Core-Based Systems-on-a-Chip
by Qiang Xu, Nicola Nicolici — 2003 — in Proc. DATE Conf., 2003
…Delay Fault Testing of Core-Based Systems-on-a-Chip Qiang Xu and Nicola Nicolici Department…
Cited by 1 (0 self) – Add To MetaCart

Time/Area tradeoffs in testing hierarchical SOCs with hard mega-cores
by Qiang Xu, Nicola Nicolici — 2004 — Proc. ITC
… and Nicola Nicolici Department of Electrical and Computer Engineering McMaster University, Hamilton, ON L8S 4…
Cited by 3 (0 self) – Add To MetaCart

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
by Nicola Nicolici And, Nicola Nicolici, Bashir M. Al-hashimi — 2000 — In Proc. IEEE International Test Conference (ITC 2000
…Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths Nicola Nicolici and Bashir M…
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Multiple Scan Chains for Power Minimization During Test Application in Sequential Circuits
by Nicola Nicolici, Bashir M. Al-hashimi — 2002 — IEEE Computer
…Multiple Scan Chains for Power Minimization During Test Application in Sequential Circuits Nicola…
Cited by 10 (1 self) – Add To MetaCart

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
by Nicola Nicolici, Bashir M. Al-hashimi — 2000 — In Proc. IEEE International Test Conference (ITC 2000
…Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths Nicola Nicolici and Bashir M…
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Power Constrained Test Scheduling Using Power Profile Manipulation
by Paul Rosinger, Bashir Al-Hashimi, Nicola Nicolici — 2001 — In Proceedings International Symposium on Circuits and Systems (ISCAS), volume V
…-Hashimi, and Nicola Nicolici ABSTRACT This paper presents a novel power profile manipulation technique which reduces…
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Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
by Nicola Nicolici, Bashir M. Al-hashimi — 1999 — In Proc. IEEE/ACM Design Automation and Test in Europe (DATE 99
…Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths Nicola…
Cited by 4 (3 self) – Add To MetaCart

Power profile manipulation: a new approach for reducing test application time under power constraints
by Paul M. Rosinger, Paul M. Rosinger, Bashir M. Al-hashimi, Bashir M. Al-hashimi, Nicola Nicolici, Nicola Nicolici — 2002 — IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
… Constraints Paul M. Rosinger , Bashir M. Al-Hashimi and Nicola Nicolici TCAD paper no.: 51 Accepted…
Cited by 7 (0 self) – Add To MetaCart

Hardware/Software Co-Testing of Embedded Memories in Complex SOCs
by Bai Hong Fang, Qiang Xu, Nicola Nicolici — 2003 — In Proc. International Conference on Computer-Aided Design (ICCAD
… and Nicola Nicolici Department of Electrical and Computer Engineering McMaster University, Hamilton, ON L8S 4…
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Variable-length Input Huffman Coding for System-on-a-Chip Test
by Paul T. Gonciari, Paul T. Gonciari, Bashir M. Al-hashimi, Bashir M. Al-hashimi, Nicola Nicolici, Nicola Nicolici — 2003 — IEEE Trans. on Computer-Aided Design
…-Hashimi, and Nicola Nicolici Paper no. 556 Accepted for publication as a Transaction Brief Paper Submitted: July 2002…
Cited by 12 (1 self) – Add To MetaCart

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