Searching for authors named "Mick Tegethoff" – sorted by Relevance.
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ASIC Manufacturing Test Cost Prediction at Early Design Stage
- ASIC Manufacturing Test Cost Prediction at Early Design Stage Von-Kyoung Kim 1 Tom Chen 2 Mick
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ASIC Yield Estimation At Early Design Cycle
- ASIC Yield Estimation At Early Design Cycle Vonkyoung Kim Mick Tegethoff* Tom Chen Department
- Cited by 3 (2 self) – Add To MetaCart
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MANUFACTURING TEST SIMULATOR: A CONCURRENT ENGINEERING TOOL FOR BOARDs and MCMs
- 1 MANUFACTURING TEST SIMULATOR: A CONCURRENT ENGINEERING TOOL FOR BOARDs and MCMs Mick M
- Cited by 2 (1 self) – Add To MetaCart
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On Clustering Of Defects And Yield Of Smt Assemblies
- 1 ON CLUSTERING OF DEFECTS AND YIELD OF SMT ASSEMBLIES Mick M.V. Tegethoff Hewlett
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Defects, Fault Coverage, Yield And Cost, In Board Manufacturing
- AND COST, IN BOARD MANUFACTURING Mick M.V. Tegethoff * Hewlett--Packard Company 3404 E. Harmony Rd., Fort
- Cited by 1 (0 self) – Add To MetaCart

