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33 documents found, showing 1 through 10. Next 10 →

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Fast Cross-sectional Display of Large Data Sets
by V. J. Dercksen, S. Prohaska, H. -c. Hege
… sets which are too large to fit into main memory, this is an expensive operation as each slice…
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Real Value for Minimal Cost: Formal Verification of a Distributed Shared Memory Cache Coherence
by Cindy Eisner — 1996 — Protocol (A Case Study); IBM Science and Technology, Haifa Research Laboratory
…-processor (TCMP) consisting of a number of processors and a slice of main memory, with the addition of a coupling…
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Low power coarse-grained reconfigurable instruction set processor
by Francisco Barat, Murali Jayapala, Tom Vander, Aa Geert, Deconinck Rudy Lauwereins, Henk Corporaal — 2003 — In 3th Intl. Conf. on Field Programmable Logic and Applications
… To External Memory Unified L2 Cache Slice 0 Conf. Mem. PE PE Slice 1 PE PE RF Conf. Mem. PE PE Slice 2 PE PE…
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Interfacing the MoM-PDA to an Internet-based Development System
by Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber — Proc. of the HICSS-32
… in slices and mapping them on different memory modules. Because of the limited number of memory banks…
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The Real-time Interactive Visible Human Navigator
by Sebastian Gerlach Roger, Roger D. Hersch — IEEE INTERNET COMPUTING http://computer.org/internet/ MARCH • APRIL
… of the final extracted slices since all extents required for slice display have to be available in memory…
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Defect Analysis And Realistic Fault Model Extensions For Multi-Port SRAMS
by Pradeep Nagaraj Shambhu, Pradeep Nagaraj, Shambhu Upadhyaya, Kamran Zarrineh, Dean Adams — 2001 — SRAMS”, 10 th IEEE North Atlantic Test Workshop
… In this paper, we consider the SRAM electrical fault model for multi-port memories. A memory slice consisting…
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Power-aware RAM mapping for FPGA embedded memory blocks
by Russell Tessier — 2006 — In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays
… is an example of vertical memory slicing. In general, an FPGA embedded memory block can be structured to have a…
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Optimized Address Assignment for DSPs with SIMD Memory Accesses
by Markus Lorenz, David Kottmann, Steven Bashford, Rainer Leupers, Peter Marwedel — 2001 — In Proceedings of the ASP-DAC
… slice 0 15 1 ABCD ABCD AGU WideDataMemory(GroupMemory) (16x16)bit Fig. 1: Architecture of the M3-DSP…
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A massively scaleable decoder architecture for low-density parity-check codes
by Gwan Choi, Krishna Narayanan, Abhiram Prabhakar, Euncheol Kim — 2003 — in Proceedings IEEE Int Symp. on Circuits and Systems 2003 (ISCAS03
…- To route the information to and from the appropriate memory slices. d) Parallelizing Constraints…
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Defect Analysis And Realistic Fault Model Extensions For Multi-Port SRAMs
by Pradeep Nagaraj, Pradeep Nagaraj — 2001
… 16 Hierarchical View Of Slice Of Memory…………………………………… 27 17 Defects In A 4-Cell SRAM Array…
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