Searching for authors named "Mehrdad Nourani" – sorted by Relevance.
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Testing High-Speed SoCs Using LowSpeed ATEs
- Testing High-Speed SoCs Using Low-Speed ATEs Mehrdad Nourani Center for Intergrated Circuits
- Cited by 2 (0 self) – Add To MetaCart
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Avoiding False Paths Caused by Resource Binding in RTL Delay Analysis
- Avoiding False Paths Caused by Resource Binding in RTL Delay Analysis Mehrdad Nourani y
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A Layout Estimation Algorithm for RTL Datapaths
- A Layout Estimation Algorithm for RTL Datapaths y Mehrdad Nourani and Christos Papachristou
- Cited by 6 (2 self) – Add To MetaCart
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Nine-Coded Compression Technique with Application toReduced Pin-Count Testing and Flexible On-Chip Decompression
- -Chip Decompression Mohammad Tehranipour, Mehrdad Nourani Center for Integrated Circuits & Systems The Univ. of Texas
- Cited by 9 (2 self) – Add To MetaCart
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SoC test scheduling with power-time tradeoff and hot spot avoidance
- SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance James Chin and Mehrdad Nourani
- Cited by 5 (1 self) – Add To MetaCart
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Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems
- Systems y Mehrdad Nourani and Christos Papachristou Department of Computer Engineering Case Western
- Cited by 1 (1 self) – Add To MetaCart
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False Path Exclusion in Delay Analysis of RTL-Based Datapath Controller Designs
- in Delay Analysis of RTL�Based Datapath�Controller Designs y Mehrdad Nourani z In this paper� we present
- Cited by 3 (0 self) – Add To MetaCart
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Test Pattern Generation for Signal Integrity Faults on Long Interconnects
- ], an on-line detection of realistic failures including crosstalk, Mehrdad Nourani Center for Integrated
- Cited by 10 (2 self) – Add To MetaCart
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Built-In Self-Test for Signal Integrity
- Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic methodology to model and test signal integrity in deep-submicron high-speed interconnects which bind the internal cores to one another. We combined various signal integrity
- Cited by 11 (2 self) – Add To MetaCart
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Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
- -drop [7][11], inserting buffers on the interconnects Mehrdad Nourani and Amir Attarha Center
- Cited by 7 (0 self) – Add To MetaCart

