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Searching for authors named "Manolis Katevenis" – sorted by Relevance.

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  • Scheduling in non-blocking buffered three-stage switching fabrics  
  • by Nikos Chrysos, Manolis Katevenis — 2006 — Proceedings of IEEE INFOCOM
  • …Abstract — Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion management, however, is the central open problem; without it, performance suffers heavily under real-world traffic patterns. Schedulers …
  • Cited by 2 (0 self) – Add To MetaCart
  • Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks  
  • by Aggelos Ioannou, Manolis, Manolis Katevenis — 2001 — In IEEE/ACM Transactions on Networking
  • …Quality-of-Service (QoS) guarantees in networks are increasingly based on per-flow queueing and sophisticated scheduling. Most advanced scheduling algorithms rely on a common computational primitive: priority queues. Large priority queues are built using calendar queue or heap data structures. To su…
  • Cited by 8 (0 self) – Add To MetaCart
  • Weighted Fairness in Buffered Crossbar Scheduling  
  • by Nikos Chrysos, Manolis Katevenis — 2003 — Proc. IEEE HPSR’03
  • …Abstract — The crossbar is the most popular packet switch architecture. By adding small buffers at the crosspoints, important advantages can be obtained: (1) Crossbar scheduling is simplified. (2) High throughput is achievable. (3) Weighted scheduling becomes feasible. In this paper we study the fai…
  • Cited by 8 (1 self) – Add To MetaCart
  • Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters  
  • by Evangelos Markatos, Manolis G. H. Katevenis — 1996 — In Proceedings of the Second International Symposium on High-Performance Computer Architecture
  • …Networks of workstations and high-performance microcomputers have been rarely used for running highperformance applications like multimedia, simulations, scientific and engineering applications, because, although they have significant aggregate computing power, they lack the support for efficient me…
  • Cited by 23 (9 self) – Add To MetaCart
  • Multi-Queue Management and Scheduling for Improved QoS in Communication Networks  
  • by Manolis Katevenis, Dimitrios Serpanos, Evangelos Markatos — 1997 — In Proceedings of the European Multimedia Microprocessor Systems and Electronic Commerce (EMMSEC’97
  • …. Quality of Service (QoS) and gigabit networking are the new dimensions that modern VLSI technology is bringing into communications, today. Highly-integrated building block components are the key in bringing this new technology to the users at low cost. Based on OMI-developed HIC/HS gigabit links, …
  • Cited by 1 (1 self) – Add To MetaCart
  • Switching Fabrics with Internal Backpressure using the Atlas I Single Chip ATM Switch  
  • by Manolis Katevenis, Dimitrios Serpanos, Emmanuel Spyridakis — 1997 — In Proceedings of the GLOBECOM’97 Conference
  • …ABSTRACT: ATLAS I is a single-chip ATM switch with optional credit-based (backpressure) flow control. This 4-million-transistor 0.35-micron CMOS chip, which is currently under development, offers 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containi…
  • Cited by 4 (1 self) – Add To MetaCart
  • VC-level Flow Control and Shared Buffering in the Telegraphos Switch  
  • by Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou, Manolis Stratakis — Proceedings of IEEE Hot Interconnects
  • …ABSTRACT: We present three implementations of a fixed-size-packet switch featuring shared buffering, virtual circuit (VC) flow control, and 3 clock cycle cutthrough latency, for applications in gigabit LAN’s, networks of workstations, multiprocessor networks, and WAN’s. VC-level credit-based flow co…
  • Cited by 1 (0 self) – Add To MetaCart
  • Vatsolaki: ‘‘ATLAS I: AGeneral-Purpose, Single-Chip ATM Switch with Credit-Based Flow  
  • by Manolis Katevenis, Dimitrios Serpanos, Panagiota Vatsolaki — 1996 — Control’’, Hot Interconnects IV Symposium
  • …ABSTRACT: ATLAS I is a 16x16 single-chip ATM switch, featuring 20 Gbit/s aggregate I/O throughput, submicrosecond cut-through latency, gigabaud serial links, link bundling, rate-based and optional credit-based flow control, 256-cell shared buffer, three service classes, 54 output queues, multicastin…
  • Cited by 2 (2 self) – Add To MetaCart
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