Searching for "MIRS Modulo Scheduling with Integrated Register Spilling." – sorted by Relevance.

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2 documents found, showing 1 through 2.

Register constrained modulo scheduling
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — IEEE Trans. Parallel Distrib. Syst
… scheduling: MIRS (Modulo Scheduling with Integrated Register Spilling). The experimental evaluation reports…
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Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — In Proceedings of the 34th Annual International Symposium on Microarchitecture
…) and the loop is scheduled again. MIRS (Modulo scheduling with Integrated Register Spilling) [33] is an approach…
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