Searching for "Logic Synthesis." – sorted by Relevance.
-
Wireplanning in Logic Synthesis
- Abstract Wireplanning in Logic Synthesis Wilsin Gosti Amit Narayan + Robert K. Brayton Alberto L
- Cited by 13 (2 self) – Add To MetaCart
-
Booledozer: Logic synthesis for ASICs
- BooleDozer : Logic synthesis for ASICs L. Stok D. S. Kung D. Brand A. D. Drumm A. J. Sullivan L. N
- Cited by 8 (1 self) – Add To MetaCart
-
LOGIC SYNTHESIS FOR LOW POWER
- Chapter 1 LOGIC SYNTHESIS FOR LOW POWER Luca Benini DEIS - Universita di Bologna lbenini
- Add To MetaCart
-
Secure Logic Synthesis
- Secure Logic Synthesis Kris Tiri 1 and Ingrid Verbauwhede 1,2 1 UC Los Angeles, 2 K.U.Leuven {tiri
- Cited by 1 (0 self) – Add To MetaCart
-
Metrics for structural logic synthesis
- Metrics for Structural Logic Synthesis Prabhakar Kudva Andrew Sullivan William Dougherty IBM TJ
- Cited by 11 (1 self) – Add To MetaCart
-
Logic Synthesis and Verification Algorithms
- LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS by Gary D. Hachtel University of Colorado Fabio
- Cited by 107 (0 self) – Add To MetaCart
-
Reversible Logic Synthesis
- REVERSIBLE LOGIC SYNTHESIS by DMITRI MASLOV M.Sc. (Mathematics) Lomonosov’s Moscow State
- Cited by 2 (1 self) – Add To MetaCart
-
Logic Synthesis of Reversible Wave Cascades
- Logic Synthesis of Reversible Wave Cascades Abstract A circuit is reversible if it maps each input
- Cited by 19 (6 self) – Add To MetaCart
-
Small but Nasty Logic Synthesis Examples
- Small but Nasty Logic Synthesis Examples Petr Fiˇser, Jan Schmidt Czech Technical University
- Add To MetaCart
-
Congestion-Aware Logic Synthesis
- Congestion-Aware Logic Synthesis Davide Pandini † , Lawrence T. Pileggi ‡ , and Andrzej J
- Add To MetaCart

