Searching for "Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality" – sorted by Relevance.

Order by: Citations | Year (Descending) | Year (Ascending) | Recency

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB

1 documents found, showing 1 through 1.

Logic Design for On-Chip Test Clock Generation
by Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl — 2005 — Implementation Details and Impact on Delay Test Quality,” Proc. Design Automation & Test Conference Europe
…Logic Design for On-Chip Test Clock Generation – Implementation Details and Impact on Delay Test…
Cited by 4 (0 self) – Add To MetaCart

Showing 1 through 1.

Try your query at: Scholar | Yahoo! | Ask | MS Live | CSB