Searching for "Latency-Guided On-Chip Bus-Network Design." – sorted by Relevance.
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Hardware-Software Co-Design of Resource Constrained Systems on Chip in a Deep Submicron Technology
- …. 2002, pp. 649-660. [19] M. Drinic, D. Kirovski, S. Meguerdichian, M. Potkonjak, “Latency-Guided On-Chip…
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