Searching for authors named "Kris Gaj" – sorted by Relevance.
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Very compact FPGA implementation of the AES algorithm
- Very Compact FPGA Implementation of the AES Algorithm Pawe̷l Chodowiec and Kris Gaj George Mason
- Cited by 11 (0 self) – Add To MetaCart
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Implementation of the Twofish Cipher Using FPGA Devices
- Implementation of the Twofish Cipher Using FPGA Devices Pawel Chodowiec, Kris Gaj pchodowi
- Cited by 2 (0 self) – Add To MetaCart
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Hardware performance of the AES finalists - survey and analysis of results
- 1. Introduction Hardware performance of the AES finalists - survey and analysis of results Kris
- Cited by 4 (3 self) – Add To MetaCart
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Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays
- Programmable Gate Arrays Kris Gaj and Pawel Chodowiec George Mason University, Electrical and Computer
- Cited by 23 (5 self) – Add To MetaCart
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Reconfigurable hardware implementation of mesh routing in number field sieve factorization”, Special Purpose Hardware for Attacking Cryptographic Systems
- Sashisu Bajracharya 1 , Deapesh Misra 1 , Kris Gaj 1 , Tarek El-Ghazawi 2 1 ECE Department, George Mason
- Cited by 1 (1 self) – Add To MetaCart
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Implementation of elliptic curve cryptosystems over GF (2 n ) in optimal normal basis on a reconfigurable computer
- Reconfigurable Computer Sashisu Bajracharya 1 , Chang Shu 1 , Kris Gaj 1 , Tarek El-Ghazawi 2 1 ECE Department
- Cited by 3 (2 self) – Add To MetaCart
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An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers
- -Purpose Reconfigurable Computers Allen Michalski 1 , Kris Gaj 1 , Tarek El-Ghazawi 2 1 ECE Department, George Mason
- Cited by 1 (1 self) – Add To MetaCart
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Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board
- Pawel Chodowiec 1 , Kris Gaj 1 , Peter Bellows 2 , and Brian Schott 2 1 Electrical and Computer
- Cited by 16 (4 self) – Add To MetaCart
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Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
- of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits > KRIS GAJ, EBY G. FRIEDMAN, AND MARC J
- Cited by 8 (7 self) – Add To MetaCart
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Functional Modeling of RSFQ Circuits Using Verilog HDL
- Functional Modeling of RSFQ Circuits Using Verilog HDL Kris Gaj, Chin-Hong Cheah + , Eby G
- Cited by 2 (2 self) – Add To MetaCart

