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Searching for authors named "Koji Inoue" – sorted by Relevance.

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14 documents found, showing 1 through 10. Next 10 →

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High-Performance Low-Power Cache Memory Architectures
by Koji Inoue — 2001
…High-Performance Low-Power Cache Memory Architectures Koji Inoue Kyushu University January 2001…
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A history-based i-cache for low-energy multimedia applications
by Koji Inoue — 2002 — In Proceedings of the 2002 International Symposium on Low Power Electronics and Design
…A History-Based I-Cache for Low-Energy Multimedia Applications ABSTRACT Koji Inoue Dept. of Elec…
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Abstract Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption
by Koji Inoue, Tohru Ishihara, Kazuaki Murakami
…Abstract Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption Koji…
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Trends in High-Performance, Low-Power Cache Memory Architectures
by Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami — 2001 — IEICE Transactions on Electronics
… Memory Architectures Koji INOUE † , Nonmember, Vasily G. Moshnyaga † , and Kazuaki MURAKAMI †† , Members…
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Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors
by Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami — 2001 — In Asia-Pacific Conference on ASICs
…-Performance, Low-Power Microprocessors Koji INOUE † , Vasily G. Moshnyaga † , and Kazuaki MURAKAMI †† , Members…
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On-Chip Memorypath Architectures for Parallel Processing RAM (PPRAM)
by Hiroshi Miyajima, Koji Inoue, Koji Kaiy, Kazuaki Murakami — 1997 — RAM (PPRAM)”, Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, 24th International Symposium on Computer Architecture
…On-Chip Memorypath Architectures for Parallel Processing RAM (PPRAM) Hiroshi Miyajima, Koji Inoue…
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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
by Koji Inoue, Koji Kaiy, Kazuaki Murakami — 1998 — Japanese IEICE Transactions on Electronics
…High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs Koji Inoue, Koji…
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Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs
by Koji Inoue, Koji Kai, Kazuaki Murakami — 1999
…/Logic LSIs Koji Inoue y Koji Kai z Kazuaki Murakami y y Dept. of Computer Science and Comm. Eng. Kyushu…
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A Low Energy Set–Associative I–cache with Extended BTB
by Koji Inoue, Vasily G. Moshnyaga — 2002 — in Proceedings of the International Conference on Computer Design (ICCD), 2002
…A Low Energy Set-Associative I-Cache with Extended BTB Koji Inoue, Vasily G. Moshnyaga Dept…
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Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints
by Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami — 2002 — In 2nd International Workshop on Power-Aware Computing Systems
… Footprints Abstract Koji Inoue†, Vasily Moshnyaga†, and Kazuaki Murakami‡ †Department of Computer Science…
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