MetaCart Sign in to MyCiteSeerX

Documents
Authors
Tables !

Searching for "Kilo-instruction Processors." – sorted by Relevance.

Order by: Citations | Year (Descending) | Year (Ascending) | Recency

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB

10 documents found, showing 1 through 10.

ATOM

Toward kilo-instruction processors
by Adrián Cristal, Oliverio J. Santana, Oliverio J. Santana, Mateo Valero, Mateo Valero — 2004 — ACM Transactions on Architecture and Code Optimization
…Toward Kilo-instruction Processors ADRIÁN CRISTAL, OLIVERIO J. SANTANA, and MATEO VALERO…
Cited by 22 (3 self) – Add To MetaCart

A decoupled kilo-instruction processor
by Miquel Pericàs, Adrian Cristal, Ruben González, Daniel A. Jiménez, Mateo Valero — 2006 — In Proceedings of the Twelfth International Symposium on High Performance Computer Architecture
…A Decoupled KILO–Instruction Processor Miquel Pericàs †⋆ , Adrian Cristal †⋆ , Ruben González…
Cited by 5 (1 self) – Add To MetaCart

A first glance at kilo-instruction based multiprocessors
by Marco Galluzzi, Ramón Beivide, Valentín Puente — 2004 — in CF’04: Proceedings of the first conference on Computing Frontiers
… as Kilo-instruction processors [8]. When running numerical applications, Kilo-instruction processors have…
Cited by 4 (1 self) – Add To MetaCart

Implementing kilo-instruction multiprocessors
by Enrique Vallejo, Marco Galluzzi, Adrián Cristal, O Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero, Grupo De Arquitectura De Computadores — 2005 — In Proceedings of the 2005 IEEE International Conference on Pervasive Services
…. Later, in [10] the idea of having a multiprocessor composed of Kilo-Instruction Processors, which…
Cited by 7 (1 self) – Add To MetaCart

A Two-Level Load/Store Queue Based on Execution Locality
by Miquel Pericàs, Adrian Cristal, Francisco J. Cazorla, Ruben González, Alex Veidenbaum, Daniel A. Jiménez, Mateo Valero
…-wall by implementing kilo-instruction windows. Large window processors require large Load/Store Queues that would…
Cited by 1 (0 self) – Add To MetaCart

Finding parallelism for future epic machines
by Matthew Iyer, Chinmay Ashok, Joshua Stone, Neil Vachharajani, Daniel A. Connors, Manish Vachharajani — 2005 — in Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing Techniques
… by kilo-instruction window processors [10]) and distant ILP (due to instructions more well over 2K…
Cited by 3 (2 self) – Add To MetaCart

Chip multi-processor scalability for single-threaded applications
by Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel Connors — 2005 — In Proceedings of the Workshop on Design, Architecture, and Simulation of Chip MultiProcessors
… more time. Techniques such as kilo-instruction processors [7], [9] attempt to overcome this in…
Cited by 6 (1 self) – Add To MetaCart

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
by Sanghyun Park, Aviral Shrivastava, Yunheung Paek
… mechanisms [25] and Window Instruction Buffer (WIB) [20]. Also Kilo-instruction processors [8] have been…
Add To MetaCart

A Flexible Heterogeneous Multi-Core Architecture
by Miquel Pericàs, Adrian Cristal, Francisco J. Cazorla, Ruben González, Daniel A. Jiménez, Mateo Valero
… latencies. 3.2 Our Baseline: The D-KIP The Decoupled KILO-Instruction Processor (D-KIP) [23] design…
Cited by 4 (0 self) – Add To MetaCart

Optimizing dual-core execution for power efficiency and transientfault recovery
by Yi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou, Ieee Computer Society — 2007 — IEEE Trans. on Parallel and Distributed Systems
… decoupled kilo-instruction processors [24]. Run-ahead execution [12], [23] is another alternative to large…
Cited by 3 (1 self) – Add To MetaCart

Showing 1 through 10.

ATOM

Try your query at: Scholar | Yahoo! | Ask | MS Live | CSB