Searching for authors named "Keikichi Tamaru" – sorted by Relevance.
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A Floorplan Based Methodology for Data-Path Synthesis of Sub-micron ASICs
- Vasily G.MOSHNYAGA y and Keikichi TAMARU y , Members SUMMARY As IC fabrication technology enters a
- Cited by 6 (0 self) – Add To MetaCart
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P2Lib: T. Sakurai, and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, no. 4, pp. 887-893, Apr. 1991.
- Kitamura, and Keikichi Tamaru Department of Electronics and Communication, Kyoto University Sakyo-ku, Kyoto
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Estimation of Short-Circuit Power Dissipation for Static CMOS Gates
- Gates Akio Hirata y , Hidetoshi Onodera y and Keikichi Tamaru y , Members SUMMARY We present a
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Estimation of Propagation Delay considering Short-Circuit Current for Static CMOS Gates
- -Circuit Current for Static CMOS Gates Akio Hirata, Hidetoshi Onodera and Keikichi Tamaru Abstract--- We present
- Cited by 3 (0 self) – Add To MetaCart
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Estimation of Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load
- Hirata, Hidetoshi Onodera and Keikichi Tamaru Department of Electronics and Communications, Kyoto
- Cited by 9 (1 self) – Add To MetaCart
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A Memory-based Parallel Processor for Vector Quantization: FMPP-VQ
- KOBAYASHI y , Member, Masayoshi KINOSHITA y3 , Nonmember, Hidetoshi ONODERA y , and Keikichi TAMARU
- Cited by 2 (0 self) – Add To MetaCart
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Proposal of a Timing Model for CMOS Logic Gates Driving a CRC pi Load
- Onodera and Keikichi Tamaru Department of Communications and Computer Engineering Kyoto University, Sakyo
- Cited by 1 (0 self) – Add To MetaCart
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Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC pi Load
- Dissipation for Static CMOS Gates Driving a CRC �� Load Akio Hirata y , Hidetoshi Onodera y and Keikichi
- Cited by 1 (1 self) – Add To MetaCart
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Estimation Of Short-Circuit Power Dissipation And Its Influence On Propagation Delay For Static Cmos Gates
- CMOS GATES Akio Hirata, Hidetoshi Onodera and Keikichi Tamaru Department of Electronics
- Cited by 2 (1 self) – Add To MetaCart
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Register-Transfer Module Selection for Sub-micron ASIC Design
- .MOSHNYAGA y , Yutaka MORI y , Nonmembers and Keikichi TAMARU y , Member SUMMARY In order to shorten
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