Searching for authors named "Juan Lanchares" – sorted by Relevance.
3 documents found, showing 1 through 3.
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A Pseudo Delay-Insensitive Timing Model to Synthesising Low-Power Asynchronous Circuits
- … Garnica, Juan Lanchares, Roman Hermida Universidad Complutense de Madrid. Dpto. Arquitectura de…
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Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches ⋆
- … H. Albonesi 3 , Oscar Garnica 1 , and Juan Lanchares 1 1 Departamento de Arquitectura de…
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FPGA Placement by Thermodynamic Combinatorial Optimization
- …FPGA Placement by Thermodynamic Combinatorial Optimization Juan De Vicente , Juan Lanchares 2, Rom…
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Showing 1 through 3.
