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Searching for authors named "Josep Llosa" – sorted by Relevance.

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36 documents found, showing 1 through 10. Next 10 →

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Reducing The Impact Of Register Pressure On Software Pipelined Loops
by Josep Llosa, Margarita Espuny — 1996
…REDUCING THE IMPACT OF REGISTER PRESSURE ON SOFTWARE PIPELINED LOOPS Josep Llosa UPC. Universitat…
Cited by 12 (8 self) – Add To MetaCart

Memory Controlled Spill Code for Software Pipelining
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — 1999
… Spill Code for Software Pipelining Javier Zalamea, Josep Llosa, Eduard Ayguad'e and Mateo Valero…
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An Efficient Solver for Cache Miss Equations
by Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa — 2000 — In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'00
…An Efficient Solver for Cache Miss Equations Nerina Bermudo, Xavier Vera, Antonio Gonz'alez, Josep…
Cited by 9 (8 self) – Add To MetaCart

Near-Optimal Padding for Removing Conflict Misses
by Xavier Vera, Josep Llosa, Antonio Gonzalez — 2002 — In Languages and Compilers for Parallel Computers
…Near-Optimal Padding for Removing Conflict Misses Xavier Vera , Josep Llosa 2, and Antonio…
Cited by 6 (3 self) – Add To MetaCart

Reduced Code Size Modulo Scheduling in the Absence of Hardware Support
by Josep Llosa, Josep Llosa, Stefan M. Freudenberger, Stefan M. Freudenberger — 2002 — In Proceedings of the 35th Annual International Symposium on Microarchitecture
…Reduced Code Size Modulo Scheduling in the Absence of Hardware Support Josep Llosa 1 , Stefan M…
Cited by 4 (0 self) – Add To MetaCart

Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — In Proceedings of the 34th Annual International Symposium on Microarchitecture
…, Josep Llosa, Eduard Ayguade and Mateo Valero Departament d'Arquitectura de Computadors (UPC…
Cited by 21 (5 self) – Add To MetaCart

Hierarchical clustered register file organization for VLIW processors
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — 2003 — International Parallel and Distributed Processing Symposium, 2003. Proceedings. 22-26 April 2003 Page(s):10
…Hierarchical Clustered Register File Organization for VLIW Processors Javier Zalamea, Josep Llosa…
Cited by 6 (0 self) – Add To MetaCart

Resource widening versus replication: limits and performance-cost trade-off
by David López, Josep Llosa, Mateo Valero, Eduard Ayguadé — 1998 — 12 International Conference on SupercomputingJuly
…, Josep Llosa, Mateo Valero and Eduard Ayguadé Abstract A balanced increase of memory bandwidth…
Cited by 1 (1 self) – Add To MetaCart

Register constrained modulo scheduling
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — IEEE Trans. Parallel Distrib. Syst
… Constrained Modulo Scheduling Javier Zalamea, Josep Llosa, Eduard Ayguadé, and Mateo Valero, Fellow, IEEE…
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Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures
by Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero — 2001 — In Proc. of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT
… Javier Zalamea, Josep Llosa, Eduard Ayguad'e and Mateo Valero (*) Abstract--- High…
Cited by 6 (0 self) – Add To MetaCart

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