Searching for authors named "James Irvine" – sorted by Relevance.
4 documents found, showing 1 through 4.
-
A design flow for partially reconfigurable hardware
- …This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing…
- Cited by 8 (0 self) – Add To MetaCart
-
Characteristics of wap traffic
- …Strathprints is designed to allow users to access the research…
- Cited by 3 (0 self) – Add To MetaCart
-
Timing Verification of Dynamically Reconfigurable Logic For The Xilinx Virtex FPGA Series
- …This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves…
- Cited by 1 (1 self) – Add To MetaCart
-
Multi-User FPGA Co-Simulation Over TCP/IP
- …FPGA Co-simulation of an IP core is an important design flow step in IP and System Development. In this paper we discuss how, with Xilinx's System Generator for DSP 3.1 (XSG), it is possible for multiple-users to hardware cosimulate IP cores over any distance via TCP/IP, sharing only one FPGA board …
- Add To MetaCart
Showing 1 through 4.
