Searching for authors named "Irith Pomeranz" – sorted by Relevance.
31 documents found, showing 1 through 10.
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Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits
- …, USA. Copyright 2001 ACM 1-58113-297-2/01/0006...$5.00. Irith Pomeranz School of Electrical & Computer…
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On Improving Genetic Optimization based Test Generation
- …-9220549, and in part by NSF Grant No. MIP-9357581 Irith Pomeranz and Sudhakar M. Reddy + Electrical…
- Cited by 3 (0 self) – Add To MetaCart
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Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
- …Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults Irith Pomeranz 1…
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On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem
- … 0-89791-821/96 $5.00 ©1996 IEEE Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer…
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On Diagnosis of Pattern-Dependent Delay Faults
- … and/or a fee. DAC 2000, Los Angeles, California (c) 2000 ACM 1-58113-188-7/00/0006..$5.00 Irith…
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Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
- …. In addi- + Research supported in part by NSF Grant No. MIP-9725053. Irith Pomeranz and Sudhakar M. Reddy…
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Functional Test Generation for Full Scan Circuits
- … by NSF Grant No. MIP-9725053. Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering…
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A Synthesis Procedure for Flexible Logic Functions
- …-9601503. Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer Engineering Department University…
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On Minimizing the Number of Test Points Needed to Achieve Complete Robust Path Delay Fault Testability
- … Testability Prasanti Uppaluri Uwe Sparmann y Irith Pomeranz z Avant! Corporation Computer Science Dept…
- Cited by 4 (1 self) – Add To MetaCart
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A New Approach to Test Generation and Test Compaction for Scan Circuits
- …A New Approach to Test Generation and Test Compaction for Scan Circuits Irith Pomeranz 1…
- Cited by 2 (0 self) – Add To MetaCart
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