Searching for authors named "Huiyang Zhou" – sorted by Relevance.

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15 documents found, showing 1 through 10. Next 10 →

Dual-core execution: Building a highly scalable single-thread instruction window
by Huiyang Zhou — 2005 — In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
…Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window Huiyang Zhou…
Cited by 27 (2 self) – Add To MetaCart

Branch Prediction by Combining Multiple Partial Matches
by Hongliang Gao, Huiyang Zhou — 2006 — In the 2nd JILP Championship Branch Prediction Competition (CBP-2
…: Prediction by Combining Multiple Partial Matches Hongliang Gao HGAO@(email omitted); Huiyang Zhou ZHOU…
Cited by 2 (0 self) – Add To MetaCart

Unified Architectural Support for Soft-Error Protection or Software Bug Detection
by Martin Dimitrov, Huiyang Zhou
… Huiyang Zhou School of Electrical Engineering and Computer Science University of Central Florida {dimitrov…
Cited by 2 (0 self) – Add To MetaCart

Code Size Efficiency in Global Scheduling for VLIW/EPIC Style Embedded Processors
by Huiyang Zhou, Huiyang Zhou, Thomas M. Conte, Thomas M. Conte — 2002 — Processors, in "The 6th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6) held in
…: Code Size Efficiency in Global Scheduling for VLIW/EPIC Style Embedded Processors Authors: Huiyang Zhou…
Cited by 8 (1 self) – Add To MetaCart

Enhancing Memory Level Parallelism via Recovery-Free Value Prediction
by Huiyang Zhou, Thomas M. Conte — 2003 — In Proceedings of the 17th International Conference on Supercomputing
…Enhancing Memory Level Parallelism via Recovery-Free Value Prediction Huiyang Zhou Thomas M. Conte…
Cited by 22 (3 self) – Add To MetaCart

Performance modeling of memory latency hiding techniques
by Huiyang Zhou, Thomas M. Conte — 2002
…Performance Modeling of Memory Latency Hiding Techniques Huiyang Zhou Thomas M. Conte Department…
Cited by 2 (2 self) – Add To MetaCart

Code Size Efficiency in Global Scheduling for ILP Processors
by Huiyang Zhou, Thomas M. Conte — 2002 — in Proceedings of the 6th Annual Workshop on the Interaction between Compilers and Computer Architectures (INTERACT-6) held in conjunction with the 8th International Symposium on High Performance Computer Architecture (HPCA-8
…Code Size Efficiency in Global Scheduling for ILP Processors Huiyang Zhou Thomas M. Conte Center…
Cited by 4 (3 self) – Add To MetaCart

Using performance bounds to guide code compilation and processor design
by Huiyang Zhou, Prof Gregory, T. Byrd, Prof S — 2003
…ABSTRACT ZHOU, HUIYANG Using Performance Bounds to Guide Code Compilation and Processor Design…
Cited by 1 (1 self) – Add To MetaCart

Enhance Memory-Level Parallelism via Recovery-Free Value Prediction
by Huiyang Zhou, Thomas M. Conte — 2003 — Proc. 2003 Int’l Conf. Supercomputing (ICS-03
… via Recovery-Free Value Prediction Huiyang Zhou, Member, IEEE, and Thomas M. Conte, Fellow, IEEE…
Cited by 2 (0 self) – Add To MetaCart

ATreegion-based Unified Approach to Speculation and Predication in Global Instruction Scheduling
by Matthew Jennings, Huiyang Zhou, Thomas M. Conte — 2001
… Matthew D. Jennings 1 , Huiyang Zhou 2 , Thomas M. Conte 2 1 BOPS Inc. 2 Department of Electrical…
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