Searching for authors named "Hideo Fujiwara" – sorted by Relevance.
13 documents found, showing 1 through 10.
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Functional constraints vs. test compression in scan-based delay testing
- …,2 Hideo Fujiwara 1 1Graduate School of Information Science 2Institute for Computer Science Nara Institute…
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Test Resource Partitioning and Optimization for SOC Designs
- …Test Resource Partitioning and Optimization for SOC Designs Erik Larsson + * and Hideo Fujiwara…
- Cited by 4 (1 self) – Add To MetaCart
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Optimal System-on-Chip Test Scheduling
- …Optimal System-on-Chip Test Scheduling Erik Larsson* + and Hideo Fujiwara* Embedded Systems…
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SPIRIT: A Highly Robust Combinational Test Generation Algorithm
- …SPIRIT: A Highly Robust Combinational Test Generation Algorithm 1 Emil Gizdarski* 2 and Hideo…
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Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability
- … Yoneda†, Tetsuo Uchiyama‡ and Hideo Fujiwara† †Graduate School of Information Science, Nara Institute…
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On the acceleration of test generation algorithms
- … Generation Algorithms HIDEO FUJIWARA, SENIOR MEMBER, IEEE, AND TAKESHI SHIMONO, STUDENT MEMBER, IEEE Abstract…
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Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture
- …, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, and Jiaguang Sun Abstract—A two-stage scan…
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Testing for the Programming Circuit of SRAM-Based FPGAs
- … +++ , and Hideo FUJIWARA +++ , Members SUMMARY The programming circuit of SRAM-based FPGAs consists of two shift…
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Efficient Test Solutions for Core-based Designs
- …, Hideo Fujiwara, Fellow, IEEE, and Zebo Peng, Senior Member, IEEE Abstract—A test solution for a complex…
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Sequential Test Generation Based on Circuit Pseudo-Transformation
- …Sequential Test Generation Based on Circuit Pseudo-Transformation Satoshi Ohtake Tomoo Inoue Hideo…
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