Searching for authors named "Hideharu Amano" – sorted by Relevance.
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MAPLE chip: a processing element for a static scheduling centric multiprocessor
- † Riku Ogawa † Keisuke Iwai †† Hideharu Amano † † Keio University †† National Defense Academy Dept
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Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster
- , Tomohiro Otsuka, Hideharu Amano, Member, IEEE, Abstract— System Area Networks (SANs), which usually accept
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Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network ∗
- -Chip Network ∗ Hiroki Matsutani 1 , Michihiro Koibuchi 2 , and Hideharu Amano 1 1Keio University 2National
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Fault tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics).
- + , Toshihiro Hanawa + , Nonmembers and Hideharu Amano + , Member SUMMARY Multistage Interconnection Networks
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A Routing Algorithm for Multihop WDM Ring
- for Multihop WDM Ring Xiaoshe DONG + , Nonmember, Tomohiro KUDOH ++ , and Hideharu AMANO + , Members SUMMARY
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Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies
- Area Networks with Irregular Topologies Michihiro Koibuchi Akiya Jouraku Konosuke Watanabe Hideharu
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Routing Algorithms Based on 2D Turn Model for Irregular Networks
- Hideharu Amano Department of Computer Science, Keio University 3-14-1, Hiyoshi, Kohoku-ku, Yokohama
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The impact of path selection algorithm of adaptive routing for implementing deterministic routing
- Michihiro Koibuchi Akiya Jouraku Hideharu Amano Dept. of Information and Computer Science Keio University 3
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An LSI implementation of the Simple Serial Synchronized Multistage Interconnection Network
- KAMEI Masashi SASAHARA Hideharu AMANO Dept. of Electrical Engineering Keio University 3-14-1, Hiyoshi
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The RDT Router Chip: A versatile router for supporting a distributed shared memory
- yy , and Hideharu Amano y , Members SUMMARY JUMP-1 is currently under development by seven
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