Searching for authors named "Haris Lekatsas" – sorted by Relevance.

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12 documents found, showing 1 through 10. Next 10 →

A²BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
by Jörg Henkel, Haris Lekatsas — 2001
…Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consumption of interconnects starts to have a significant impact on a system's total power consumption. We present novel addres…
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Random Access Decompression using Binary Arithmetic Coding
by Haris Lekatsas, Wayne Wolf — 1999 — Data Compression Conference
…We present an algorithm based on arithmetic coding that allows decompression to start at any point in the compressed #le. This random access requirement poses some restrictions on the implementation of arithmetic coding and on the model used. Our main application area is executable code compression …
Cited by 16 (3 self) – Add To MetaCart

Code Compression for Embedded Systems
by Haris Lekatsas, Wayne Wolf — 1998
…Memory is one of the most restrictedresources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressedcode CPU, acache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must bed…
Cited by 49 (2 self) – Add To MetaCart

SAMC: A Code Compression Algorithm for Embedded Processors
by Haris Lekatsas, Wayne Wolf — 1999 — IEEE Transactions on CAD
…In this paper we present a method for reducing the memory requirements of an embedded system by using code compression. We compress the instruction segment of the executable running on the embedded system and we show how to design a run-time decompression unit to decompress code on the fly before ex…
Cited by 24 (0 self) – Add To MetaCart

Code Compression for Low Power Embedded System Design
by Haris Lekatsas, Jörg Henkel, Wayne Wolf — 2000
…We propose instruction code compression as a very efficient method for reducing power on an embedded system. Our approach is the first one to measure and optimize the power consumption of a complete SOC (System--On--a--Chip) comprising a CPU, instruction cache, data cache, main memory, data buses an…
Cited by 34 (5 self) – Add To MetaCart

Code compression for VLIW processors
by Yuan Xie, Haris Lekatsas, Wayne Wolf — 2001 — in Proceedings DCC 2001. Data Compression Conference
…Code compression is an important issue in the design of an embedded system, since memory has been one of the most restricted resources. Most of the previous work in code compression has targeted RISC architectures, although VLIW processors have gained a lot of popularity recently. In this research, …
Cited by 3 (0 self) – Add To MetaCart

Design of an One-cycle Decompression Hardware for Performance Increase in Embedded Systems
by Haris Lekatsas, Jörg Henkel, Venkata Jakkula — 2002
…Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing processorto -memory bandwidth and hence provide increased system performance. In this paper we describe our design and desig…
Cited by 8 (0 self) – Add To MetaCart

An Adaptive Dictionary Encoding Scheme for SOC Data Buses
by Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf — 2002 — Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002
…As bus lengths on multi-hundred-million transistor SOCs (Systems-On-a-Chip) grow and as inter-wire capacitances of sub-0.10u technologies increase, the resulting high switching capacitances of buses (and interconnects in general) have a non-negligible impact on the power consumption of a whole SOC. …
Cited by 3 (0 self) – Add To MetaCart

Design and Simulation of a Pipelined Decompression Architecture for Embedded Systems
by Haris Lekatsas, Jörg Henkel, Wayne Wolf — 2001 — Proc. of ISSS01
…In the past, systems utilizing code compression have been shown to be advantageous over traditional systems especially in terms of smaller memory need. However, in order to take full advantage of other design criteria like increasing performance and/or minimizing power consumption, the decompressio…
Cited by 4 (0 self) – Add To MetaCart

Arithmetic Coding for Low Power Embedded System Design
by Haris Lekatsas, Jörg Henkel, Wayne Wolf — 2000 — the Proceedings of the 2000 IEEE Data Compression Conference
…We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumption. The target application area is embedded systems, where power consumption is increasingly becoming a dominant design c…
Cited by 3 (1 self) – Add To MetaCart

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