Searching for authors named "Giles Powell" – sorted by Relevance.

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3 documents found, showing 1 through 3.

Cyclone: a low-cost, high-performance FPGA
by Paul Leventis, Mark Chan, Michael Chan, David Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello — 2003 — In Proceedings of the IEEE 2003 CICC
…This paper describes the Altera Cyclone ™ FPGA, an architecture specifically designed for low-cost, high-volume applications. An optimized routing architecture, simplified I/O structure, and carefully selected features combine to yield a 57 % die size reduction relative to a Stratix ™ device of simi…
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The Stratix
by Tm Routing And, David Lewis, Vaughn Betz, David Jefferson, Andy Lee, Chris Lane, Paul Leventis, Y Marquardt, Cameron Mcclintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose — 2003 — in International symposium on Field-programmable gate arrays
…This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on…
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The stratix ii logic and routing architecture
by David Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Galloway, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis, Cameron Mcclintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose — 2005 — In FPGA ’05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
…This paper describes the Altera Stratix II ™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventi…
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