Searching for "Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs." – sorted by Relevance.

Order by: Citations | Year (Descending) | Year (Ascending) | Recency

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB

1 documents found, showing 1 through 1.

Gate sizing and replication to minimize the effects of virtual ground parasitic resistances
by Chanseok Hwang, Changwoo Kang, Massoud Pedram — in MTCMOS designs,” in Int. Symp. Quality Electronic Design
…Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances…
Cited by 1 (1 self) – Add To MetaCart

Showing 1 through 1.

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB