Searching for authors named "Frank Hannig" – sorted by Relevance.

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15 documents found, showing 1 through 10. Next 10 →

Energy Estimation of Nested Loop Programs
by Frank Hannig Hannig — 2002
… of Nested Loop Programs ∗ Frank Hannig University of Paderborn D-33098 Paderborn, Germany hannig…
Cited by 1 (1 self) – Add To MetaCart

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
by Frank Hannig, Jürgen Teich — 2004 — In Proceedings IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004
… Frank Hannig and Jürgen Teich Department of Computer Science 12, Hardware-Software-Co-Design, University…
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Design Space Exploration for Massively Parallel Processor Arrays
by Frank Hannig, Jürgen Teich — 2001 — Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings
…-65, c○ Springer-Verlag, 2001. Design Space Exploration for Massively Parallel Processor Arrays ⋆ Frank…
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Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms
by Frank Hannig, Jürgen Teich — 2004
… of Dynamic Piecewise Regular Algorithms Frank Hannig and Jürgen Teich {hannig, teich}@(email omitted); URL…
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Dynamic Piecewise Linear/Regular Algorithms
by Frank Hannig And, Frank Hannig, Jürgen Teich — 2004 — In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004
… Linear/Regular Algorithms Frank Hannig and Jürgen Teich Department of Computer Science 12, Hardware…
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Regular Mapping For Coarse-Grained Reconfigurable Architectures
by Frank Hannig Hritam, Frank Hannig, Hritam Dutta, Jürgen Teich — 2004 — In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Pro cessing (ICASSP 2004), volume V
… MAPPING FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURES Frank Hannig, Hritam Dutta, and Jürgen Teich…
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Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays – Constraints and Methodology
by Frank Hannig, Hritam Dutta, Jürgen Teich — 2004 — IEE Computer Society
… and Methodology Frank Hannig, Hritam Dutta, and Jürgen Teich Department of Computer Science 12, Hardware…
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Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
by Alexey Kupriyanov, Frank Hannig, Jürgen Teich — 2004 — In Proceedings of Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004
…Automatic and Optimized Generation of Compiled High-Speed RTL Simulators Alexey Kupriyanov, Frank…
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A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template
by Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich — 2006 — In Proceedings of the 2nd International Workshop on Reconfigurable Communication Centric System-on-Chips
… Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich Department of Computer Science 12, Hardware…
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Automatic FIR Filter Generation for FPGAs
by Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich — 2005 — Embedded Computer Systems: Architectures, Modeling, and Simulation, 5th International Workshop, SAMOS 2005, Proceedings, volume 3553 of Lecture Notes in Computer Science (LNCS), pages 51–61, Island of Samos
…Automatic FIR Filter Generation for FPGAs Holger Ruckdeschel, Hritam Dutta, Frank Hannig…
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