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Searching for "Formal Verification of Digital Circuits." – sorted by Relevance.

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11 documents found, showing 1 through 10. Next 10 →

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Formal Verification of Digital Circuits Using Symbolic Ternary System Models
by Randal E. Bryant, Carl-Johan H. Seger
…Formal Verification of Digital Circuits Using Symbolic Ternary System Models Randal E. Bryant…
Cited by 22 (6 self) – Add To MetaCart

Formal Methods for the Verification of Digital Circuits
by C.A.J. van Eijk, Op Gezag, Van De Rector Magnificus, Prof. Dr. M. Rem, Cornelis Arnoldus, Josephus Eijk — 1997
…Formal Methods for the Verification of Digital Circuits Formal Methods for the Verification…
Cited by 2 (1 self) – Add To MetaCart

Ordered Binary Decision Diagrams and Minimal Trellises
by John Lafferty, Alexander Vardy — 1999 — IEEE Transactions on Computers
… in computer-aided design and in formal verification of digital circuits. Minimal trellises are graphical…
Cited by 2 (1 self) – Add To MetaCart

Natural Language for Hardware Verification: Semantic Interpretation and Model Checking
by Alexander Holt, Er Holt, Ewan Klein, Claire Grover — 1999 — ILLC, University of Amsterdam
… system allows the formal verification of digital circuits using specifications expressed in English…
Cited by 3 (2 self) – Add To MetaCart

Formal Verification of PLC Programs
by M. Rausch, B.H. Krogh — 1998 — In Proc. American Control Conference
…, an established tool for formal verification of digital circuits and protocols [1, 2]. This provides a means…
Cited by 4 (0 self) – Add To MetaCart

A cache-based parallel genetic algorithm for the BDD variable ordering problem
by Umberto S. Costa, Anamaria M. Moreira, David Déharbe — 2000
… application of BDDs has been symbolic model checking, employed in the formal verification of digital circuits…
Cited by 4 (4 self) – Add To MetaCart

A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver
by J.C. Madre, O. Coudert — 1991 — in Proc. of IJCAI'91
… developed in the framework of a research project on formal verification of digital circuits. The automated…
Cited by 20 (5 self) – Add To MetaCart

Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
by M.N. Velev, R.E. Bryant — 1998
… can be either 0 or 1, has proven to be very powerful for both validation and formal verification…
Cited by 6 (4 self) – Add To MetaCart

S.: The case for analog circuit verification
by Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little — Electronic Notes Theoretical Computer Science
… verification of digital circuits. Formal verification utilizes non-determinism and state space exploration…
Cited by 3 (3 self) – Add To MetaCart

Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
by Miroslav N. Velev, Randal E. Bryant — 1998
… validation and formal verification of digital circuits [17]. Given that the simulation algorithm satisfies a…
Cited by 3 (1 self) – Add To MetaCart

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