Searching for authors named "Florentin Dartu" – sorted by Relevance.
3 documents found, showing 1 through 3.
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TETA: Transistor-Level Engine for Timing Analysis
- …: Introduction Florentin Dartu * Strategic CAD Labs Intel Corporation fdartu@(email omitted); For future CMOS…
- Cited by 10 (2 self) – Add To MetaCart
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Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
- … thickness with respect to line spacing that is made to control resistance. T Florentin Dartu Carnegie Mellon…
- Cited by 35 (2 self) – Add To MetaCart
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Timed Pattern Generation for Noise-on-Delay Calculation
- … Noise-on-delay setup Florentin Dartu Strategic CAD Labs, Intel Corporation Hillsboro, OR 97124 florentin.dartu…
- Cited by 1 (0 self) – Add To MetaCart
Showing 1 through 3.
