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Fault Tolerant CMOS Logic using Ternary Gates
- Fault tolerant CMOS logic using ternary gates. Yngvar Berg, Rene Jensen, Johannes Lomsdalen
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ASPECTS OF BALANCED TERNARY ARITHMETICS IMPLEMENTED USING CMOS RECHARGED SEMI-FLOATING GATE DEVICES
- is presented in Chapter 4. PAPER VI: Fault Tolerant CMOS Logic Using Ternary Gates This paper
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