Searching for authors named "Eugene Earlie" – sorted by Relevance.
7 documents found, showing 1 through 7.
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Aggregating Processor Free Time for Energy Reduction ∗
- …Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the processor stalls, waiting for data from the memory. Processor stall can be used to increase the throughput by temporarily s…
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Compiler-in-the-Loop ADL-driven Early Architectural Exploration ∗
- …Processor architects today critically need software tools that accurately track architectural changes made during exploration, and provide fast and quantitative feedback for each design point. Indeed, Design Space Exploration (DSE) without the compiler-in-the-loop (CIL) can be meaningless. To effect…
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Operation Tables for Scheduling in the Presence of Incomplete Bypassing
- …Register byp ssing is ap owerful and widely used feature in modernp rocessors to eliminate certain data hazards. Although comp lete byp assing is ideal forp erformance, byp assing has significantimp act on cycle time, area, andp ower consump4 on of the pq cessor. Due to the strict con…
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PBExplore: A framework for compiler-in-the-loop exploration of partial bypassing in embedded processors
- …Varying partial bypassing in pipelined processors is an effective way to make performance, area and energy tradeoffs in embedded processors. However, performance evaluation of partial bypassing in processors has been inaccurate, largely due to the absence of bypass-sensitive retargetable compilation…
- Cited by 7 (4 self) – Add To MetaCart
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Retargetable Pipeline Hazard Detection for Partially Bypassed Processors
- …the presence of Partial Bypassing”. This article extends the earlier work in several ways. It better motivates for the need of Operation Tables. It more formally and completely describes the algorithms to use Operation Tables for pipeline hazard detection. It presents more experimental results, and …
- Cited by 1 (1 self) – Add To MetaCart
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Register File Power Reduction Using Bypass Sensitive Compiler
- …Abstract—This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previous…
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Automatic Design Space Exploration of Register Bypasses in Embedded Processors
- …Register Bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area and power consumption of the processor. Recent research th…
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