Searching for authors named "Erik Jan Marinissen" – sorted by Relevance.
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[76] Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In
- 6 Erik Jan Marinissen [76] Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology
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Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip
- Member, IEEE, Krishnendu Chakrabarty, Senior Member, IEEE, and Erik Jan Marinissen, Senior Member, IEEE
- Cited by 17 (3 self) – Add To MetaCart
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Efficient Test Access Mechanism Optimization for System-on-Chip
- Chakrabarty, and Erik Jan Marinissen Abstract—Test access mechanisms (TAMs) are an important component of a
- Cited by 2 (2 self) – Add To MetaCart
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On Using IEEE P1500 SECT for Test Plug-n-Play
- On Using IEEE P1500 SECT for Test Plug-n-Play Erik Jan Marinissen Philips Research Laboratories Dept
- Cited by 9 (0 self) – Add To MetaCart
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On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
- Chakrabarty and Erik Jan Marinissen ¡ ¢ Department of Electrical & Computer Engineering £ Philips Research
- Cited by 22 (12 self) – Add To MetaCart
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Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
- ? , Krishnendu Chakrabarty y and Erik Jan Marinissen z ? IBM Microelectronics y Duke University, ECE Department z
- Cited by 4 (0 self) – Add To MetaCart
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Application of Deterministic Logic BIST on Industrial Circuits
- increase is predicted Erik Jan Marinissen 2 Part of this work has been supported by the DFG under grants Wu
- Cited by 6 (0 self) – Add To MetaCart
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Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs
- for SOCs ABSTRACT Vikram Iyengar ¡ ¡ Krishnendu Chakrabarty ¡ Erik Jan Marinissen ¢ Electrical & Computer
- Cited by 9 (4 self) – Add To MetaCart
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Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
- cost, performance 1530-1591/03 $17.00 © 2003 IEEE Sandeep Kumar Goel Erik Jan Marinissen Philips
- Cited by 9 (1 self) – Add To MetaCart
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Efficient Wrapper/TAM Co-Optimization for Large SOCs
- and Erik Jan Marinissen ¡ ¢ Department of Electrical & Computer Engineering £ Philips Research Laboratories
- Cited by 7 (6 self) – Add To MetaCart

