Searching for authors named "Eric Mercer" – sorted by Relevance.
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Trace Theoretic Verification of Timed Circuits: Correctness, Reduction, and Interpretation.
- Trace Theoretic Verication of Timed Circuits: Correctness, Reduction, and Interpretation. Eric
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Explicit state model checking with Hopper
- Explicit state model checking with Hopper Michael Jones and Eric Mercer Brigham Young University
- Cited by 3 (1 self) – Add To MetaCart
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Model checking machine code with the GNU debugger
- Model Checking Machine Code with the GNU Debugger Eric Mercer and Michael Jones Department
- Cited by 8 (2 self) – Add To MetaCart
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Modular Verification of Timed Circuits using Automatic Abstraction
- Modular Verification of Timed Circuits Using Automatic Abstraction Hao Zheng, Eric Mercer, Member
- Cited by 7 (3 self) – Add To MetaCart
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Modular synthesis of timed circuits using partial order reduction
- Modular Synthesis of Timed Circuits using Partial Order Reduction Tomohiro Yoneda ∗ Eric Mercer
- Cited by 4 (3 self) – Add To MetaCart
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Automatic Abstraction for Verification of Timed Circuits and Systems
- Automatic Abstraction for Verication of Timed Circuits and Systems ? Hao Zheng, Eric Mercer
- Cited by 2 (1 self) – Add To MetaCart
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Generating Counter-examples through Randomized Guided Search
- Generating Counter-examples through Randomized Guided Search Neha Rungta and Eric G Mercer
- Cited by 1 (0 self) – Add To MetaCart
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Title: Correctness and Reduction in Timed Circuit Verification
- Campus Drive, RM 3280 Salt Lake City, UT 84112 (801) 581-8378 EDUCATION Eric G Mercer Home Address: 625
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Improved POSET timing analysis in Timed Petri Nets
- Improved POSET Timing Analysis in Timed Petri Nets ∗ Eric G Mercer University of Utah Salt Lake
- Cited by 5 (4 self) – Add To MetaCart
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A Standard-Cell Self-timed Multiplier for Energy and Area Critical Synchronous Systems
- . Killpack Eric Mercer Chris J. Myers Electrical Engineering Department University of Utah Salt Lake City, UT
- Cited by 1 (1 self) – Add To MetaCart

