Searching for authors named "Elias Kougianos" – sorted by Relevance.

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6 documents found, showing 1 through 6.

Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
by Saraju P. Mohanty, Elias Kougianos — 2006 — in Proceedings of the 19th IEEE International Conference on VLSI Design (VLSID), 2006
…Abstract — For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation delay of behavioral level component…
Cited by 3 (3 self) – Add To MetaCart

VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking
by Saraju P. Mohanty, Elias Kougianos, N. Ranganathan — 2007
…Research in digital watermarking is mature. Several software implementations of watermarking algorithms are described in the literature, but few attempts have been made to describe hardware implementations. The ultimate objective of the research presented in this paper was to develop low-power, high…
Cited by 1 (0 self) – Add To MetaCart

A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
by Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos — 2005 — in Combinational Circuits,” in Proceedings of the 23rd IEEE International Conference of Computer Design (ICCD
…With continued and aggressive scaling, using ultralow thickness SiO2 for the transistor gates, tunneling current has emerged as the major component of leakage in CMOS circuits. In this paper, we propose a new approach called dual dielectrics of dual thicknesses (DKDT) for the reduction of both ON an…
Cited by 7 (6 self) – Add To MetaCart

Dual-k versus dual-T technique for gate leakage reduction: a comparative perspective
by Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos — in Proc. of International Symposium on Quality Electronic Design, 2006
…As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (Dual-K) or use of silicon dioxide of higher thicknesses (Dual-T) are being considered as methods for its reduct…
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PhysicalAware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits
by Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos — 2006 — In Proc of 9th IEEE Intel Conf on Design Automation and Test in Europe
…For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. …
Cited by 1 (1 self) – Add To MetaCart

A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction
by Saraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati — 2006 — In Proceedings of the 8th IEEE International Symposium on Multimedia (ISM
…In this paper we present a robust and novel strategic invisible approach for insertion-extraction of a digital watermark, a color image, into color images. The novelty of our scheme lies in determining a perceptually important sub-image in the host image so that slight tampering of the sub-image wil…
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