Searching for authors named "Dominique Borrione" – sorted by Relevance.
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A qualitative finite subset of VHDL and its semantics
- This report gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machin
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Symbolic Model Checking of VHDL Design Entities
- Model checking is gaining importance in verifying the partial specifications of complex synchronous systems modeled by means of a finite state machine. In this report, we present the principles and a tool for checking their properties in a temporal logic that allows both past and future oriented mod
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Verification of a cryptographic circuit: SHA-1 using ACL2 ∗
- Our study was motivated by a cooperative project aiming at the design and verification of a circuit for secure communications between a computer and a terminal smart card reader. A SHA-1 component is included in the circuit. SHA-1 is a cryptographic primive that produces- for any message, a 160 bits
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Validation of a Parameterized Bus Architecture Model
- In this paper, we present an experiment in the modeling of the AMBA-AHB virtual component and the proof of essential properties to validate the model. We prove the correctness of communications for an arbitrary number of masters and slaves. 1
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A functional approach to the formal specification of networks on chip
- Abstract. We present a functional approach, based on the ACL2 logic, for the specification of system on a chip communication architectures. Our decomposition of the communications allows the method to be modular for both system definition and validation. When performed in the context of the ACL2 log
- Cited by 2 (1 self) – Add To MetaCart
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Connection Errors Location and Correction in Combinational Circuits
- We present new diagnostic routines for localizing connection errors in combinational logic circuit designs. Special, diagnosis oriented, test patterns are generated in order to reduce rapidly the suspected area of the circuit where the error lies. The algorithms are implemented and the results obtai
- Cited by 5 (1 self) – Add To MetaCart
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Formal verification of VHDL using VHDL-like ACL2 models
- : When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications. The recognized need for formal verification cannot be met by current automatic equivalence and model check
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Semantics of a Verification-Oriented Subset of VHDL
- . This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machi
- Cited by 4 (1 self) – Add To MetaCart
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Design Error Diagnosis in Sequential Circuits
- . We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible
- Cited by 9 (4 self) – Add To MetaCart
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A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits
- . We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduc
- Cited by 12 (4 self) – Add To MetaCart

