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Searching for "Digit Serial Multipliers." – sorted by Relevance.

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42 documents found, showing 1 through 10. Next 10 →

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Low-Power Digit-Serial Multipliers
by Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi — 1997 — In Proc. IEEE International Symp. on Circuits and Systems (ISCAS
…LOW-POWER DIGIT-SERIAL MULTIPLIERS Yun-Nan Chang Janardhan H. Satyanarayana Keshab K. Parhi…
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Implementation Of Bit-Level Pipelined Digit-Serial Multipliers
by Krister Landern As, Krister L, Johnny Holmberg — 2004
…, Finland IMPLEMENTATION OF BIT-LEVEL PIPELINED DIGIT-SERIAL MULTIPLIERS Krister Landernäs, Johnny Holmberg…
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Design and Implementation of Low-Power Digit-Serial Multipliers
by Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi — 1997 — Proc. of the IEEE International Conference on Computer Design (ICCD
…Design and Implementation of Low-Power Digit-Serial Multipliers Yun-Nan Chang, Janardhan H…
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Digit-Serial Multiplier Design Using Skew-Tolerant Domino Circuits
by Sungwook Kim And, Sungwook Kim, Gerald E. Sobelman — 2001
…DIGIT-SERIAL MULTIPLIER DESIGN USING SKEW-TOLERANT DOMINO CIRCUITS ABSTRACT A novel connection…
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A Digit-Serial Structure for Reconfigurable Multipliers
by Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk — 2001 — Field-Programmable Logic and Applications, volume 2147 of Lecture Notes in Computer Science
…A Digit-Serial Structure for Reconfigurable Multipliers Chakkapas Visavakul, Peter Y. K. Cheung…
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Optimum digit serial GF(2 m ) multipliers for curve-based cryptography
by Eep Kumar, Thomas Wollinger, Christof Paar — 2006 — IEEE Transactions on Computers
…Optimum Digit Serial GF (2 m ) Multipliers for Curve Based Cryptography Sandeep Kumar 1 , Thomas…
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Performance Tradeoffs in Digit-Serial DSP Systems
by Hiroshi Suzuki, Yun-nan Chang, Keshab K. Parhi — 1998 — in Proc. 32nd Asilomar Conf. Signals, Systems, and Computers
…, critical paths of digit-serial multipliers cannot be reduced significantly compared to lowlatency bit…
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High-Performance Digit-Serial Complex-Number Multiplier-Accumulator
by Yun-Nan Chang, Keshab K. Parhi — 1998 — In Proceedings of ICCD
…High-Performance Digit-Serial Complex-Number Multiplier-Accumulator Yun-Nan Chang and Keshab K…
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Reducing energy in FPGA multipliers through glitch reduction
by Harold B. Lee Library, Nathaniel Wirthlin, Michael J — 2005 — BYU Dspace - https://dspace.byu.edu/handle/1877/61
…://dspace.lib.byu.edu Reducing Energy in FPGA Multipliers Through Glitch Reduction - Clock Power and Digit-Serial Addendum…
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A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
by Peter Kornerup — 1994 — IEEE Transactions on computers
… multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier…
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