Searching for authors named "Debjit Sinha" – sorted by Relevance.
8 documents found, showing 1 through 8.
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Introduction: ECE 391: Design Competition (Spring 2003)
- … rd February) 1 Debjit Sinha Arindam Mallik Somsubhra Mondal DESIGN OF A 1-BIT FULL ADDER A 1-bit full…
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Statistical Gate Sizing for Timing Yield Optimization
- …Statistical Gate Sizing for Timing Yield Optimization Debjit Sinha ECE, Northwestern University…
- Cited by 21 (6 self) – Add To MetaCart
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Optimal gate sizing for coupling-noise reduction
- …Optimal Gate Sizing for Coupling-Noise Reduction Debjit Sinha, Hai Zhou Electrical and Computer…
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A timing dependent power estimation framework considering coupling
- …A Timing Dependent Power Estimation Framework Considering Coupling Debjit Sinha ∗ , Diaa…
- Cited by 2 (0 self) – Add To MetaCart
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Smart Bit-Width Allocation for Low Power Optimization in a Systemc Based Asic Design Environment
- … Arindam Mallik, Debjit Sinha, Prith Banerjee†, Hai Zhou Electrical Engineering and Computer Science…
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Advances in computation of the maximum of a set of random variables
- …Advances in Computation of the Maximum of a Set of Random Variables Debjit Sinha, Hai Zhou…
- Cited by 4 (2 self) – Add To MetaCart
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Yield-aware cache architectures
- …Yield-Aware Cache Architectures Serkan Ozdemir Debjit Sinha * Gokhan Memik Jonathan Adams Hai Zhou…
- Cited by 8 (3 self) – Add To MetaCart
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Statistical timing yield optimization by gate sizing
- … 2006 Statistical Timing Yield Optimization by Gate Sizing Debjit Sinha, Member, IEEE, Narendra V…
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