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Searching for "Compilers for Instruction-Level Parallelism." – sorted by Relevance.

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18 documents found, showing 1 through 10. Next 10 →

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Compilers for Instruction-Level Parallelism
by Michael Schlansker, Thomas M, Kemal Ebcioglu, Ibm T. J. Watson, Jesse Z. Fang, Carol L — 1997
…. Fang Intel Corp. Carol L. Thompson Hewlett- Packard Laboratories Compilers for Instruction-Level…
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Global Trade-off between Code Size and Performance for Loop Unrolling on VLIW Architectures
by K. Heydemann, F. Bodin, P.M.W. Knijnenburg
…, are VLIW architectures that rely on the compiler to exploit Instruction Level Parallelism. Loop unrolling…
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The Multiflow Trace Scheduling Compiler
by P. Geoffrey Lowney, Stefan M. Freudenberger, Thomas J. Karzes, W. D. Lichtenstein, Robert P. Nix, John S. O’donnell, John C. Ruttenberg — 1993 — Journal of Supercomputing
… instruction-level parallelism beyond basic blocks. The compiler generates code for VLIW computers that issue…
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GURRR: A Global Unified Resource Requirements Representation
by David Berson, Rajiv Gupta, Mary Lou Soffa — 1995 — In ACM SIGPLAN Workshop on Intermediate Representations, Sigplan Notices
… of Pittsburgh Pittsburgh, Pa. 15260 Fax: (412) 624-5249 Abstract When compiling for instruction level…
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Controlled Node Splitting
by Johan Janssen, Henk Corporaal — 1996 — Compiler Construction, 6th International Conference
… splitting, compilation, instruction level parallelism. 1 Introduction In current computer architectures…
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Instruction Scheduling Using Simulated Annealing
by Philip H. Sweany, Steven J. Beaty — 1998 — In Proc. 3rd International Conference on Massively Parallel Computing Systems (MPCS '98
… an SA-driven instruction scheduler in our compiler for instruction-level parallel (ILP) architectures…
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Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
by Walter Lee Rajeev, Walter Lee, Rajeev Barua, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe — 1998 — In Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems
…Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine Walter Lee, Rajeev Barua…
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Inter-Block Code Motion without Copies
by Philip Hamilton Sweany, Philip H. Sweany — 1992
… instruction scheduling in compilers for instruction-level-parallel (ILP) architectures makes code motion even…
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Space-Time Scheduling of Instruction-Level Parallelism
by On Raw Machine, Walter Lee, Rajeev Barua, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe, Anant Agarwal — 1998 — In Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems
…Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine Walter Lee, Rajeev Barua…
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Quantifying Instruction-Level Parallelism Limits on an EPIC Architecture
by Hsien-Hsin Lee, Youfeng Wu, Gary Tyson — 2000
… that an optimizing compiler has an enormous scheduling window to exploit instruction-level parallelism (ILP) since…
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