Searching for authors named "Chrysostomos Nicopoulos" – sorted by Relevance.

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7 documents found, showing 1 through 7.

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects
by Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan, Chita R. Das
…Abstract—The notion of a Network-on-Chip (NoC) is rapidly gaining a foothold as the communication fabric in complex System-on-Chip (SoC) architectures. Scalability is the NoC's most valuable asset, which makes it ideal for larger designs. However, increasingly diminishing feature sizes have rendered…
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Exploring Fault-Tolerant Network-on-Chip Architectures
by Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan, Chita R. Das — 2006 — In Proceedings of DSN
…The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analysis of thes…
Cited by 6 (0 self) – Add To MetaCart

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
by Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, Mahmut K — 2006 — In Proceedings of ISCA-33
…Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the …
Cited by 20 (0 self) – Add To MetaCart

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
by Chrysostomos A. Nicopoulos, Dongkook Park, Jongman Kim, N. Vijaykrishnan, Mazin S. Yousif, Chita R. Das — 2006 — Proc. 39th Ann. Int. Symp. Microarchitecture (MICRO
…The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently …
Cited by 3 (1 self) – Add To MetaCart

A gracefully degrading and energy-efficient modular router architecture for on-chip networks
by Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das — 2006 — in Proc. Int. Symp. Computer Architecture
…Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint an…
Cited by 5 (0 self) – Add To MetaCart

A Hybrid SoC Interconnect with Dynamic TDMA-Based
by Transaction-Less Buses And, Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Yuan Xie, Chita Das, Vijay Degalahal — 2006 — in Proc. of the International Conference on VLSI Design
…The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Both implementations have some inherent disadvantages -- the former resulting from poor scalability and the transactional charac…
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A novel dimensionally-decomposed router for on-chip communication in 3D architectures
by Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, N. Vijaykrishnan, Mazin S. Yousif, Chita R. Das — 2007 — In Proc. of ISCA
…Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities and burgeoning die sizes in multi-core architectures. Partitioning a larger die into smaller segments and then stacking the…
Cited by 7 (1 self) – Add To MetaCart

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