Searching for authors named "Carl Ebeling" – sorted by Relevance.
-
Compiling for Coarse-Grained Adaptable Architectures
- Compiling for Coarse-Grained Adaptable Architectures 1 Carl Ebeling Department of Computer Science
- Add To MetaCart
-
The General Rapid Architecture Description
- The General Rapid Architecture Description 1 Carl Ebeling Department of Computer Science
- Add To MetaCart
-
Optimal Retiming of Multi-Phase, Level-Clocked Circuits
- Optimal Retiming of Multi-Phase, Level-Clocked Circuits 1 Brian Lockyear and Carl Ebeling
- Cited by 24 (2 self) – Add To MetaCart
-
The Practical Application of Retiming to the Design of High-Performance Systems
- and Carl Ebeling Department of Computer Science and Engineering University of Washington Seattle
- Cited by 25 (0 self) – Add To MetaCart
-
Minimizing the Effect of Clock Skew Via Circuit Retiming
- Minimizing the Effect of Clock Skew Via Circuit Retiming 1 Brian Lockyear and Carl Ebeling
- Cited by 2 (0 self) – Add To MetaCart
-
Using Precomputation in Architecture and Logic Resynthesis
- Using Precomputation in Architecture and Logic Resynthesis Soha Hassoun Carl Ebeling Tufts
- Cited by 2 (1 self) – Add To MetaCart
-
PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs
- PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs Larry McMurchie and Carl
- Cited by 90 (10 self) – Add To MetaCart
-
Mapping Tools for the Triptych FPGA
- submitted to IEEE Transactions on VLSI Systems Mapping Tools for the Triptych FPGA Carl Ebeling
- Add To MetaCart
-
Cranium: An Interface for Message Passing on Adaptive Packet Routing Networks
- Kenzie, Kevin Bolding, Carl Ebeling and Lawrence Snyder University of Washington Department of CSE, FR-35
- Cited by 19 (2 self) – Add To MetaCart
-
Architecture-Adaptive Routability-Driven Placement for FPGAs
- Architecture-Adaptive Routability-Driven Placement for FPGAs Akshay Sharma 1 , Carl Ebeling 2
- Cited by 5 (3 self) – Add To MetaCart

