Searching for authors named "Borivoje Nikolic" – sorted by Relevance.
16 documents found, showing 1 through 10.
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Design in the Power-Limited Scaling Regime
- … Technology scaling has entered a new era, where chip performance is constrained by power dissipation. Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings…
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A Single-Phase Clock HighPerformance BiCMOS
- …Abstract: A true single-phase clock BiCMOS latch intended for the use in high-performance deeply pipelined digital systems is proposed. It is based on quasi-complementary BiCMOS circuit, and uses single-phase clock. The speed and power performance of this latch are superior to previously published r…
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24.2 A 240ps 64b Carry-Lookahead Adder in 90nm CMOS
- …Fast and energy-efficient single-cycle 64b addition is essential for today’s high-performance microprocessor execution cores. The designer has several degrees of freedom to optimize the adder for performance and power. There is a choice of radix-2 or radix-4 trees, with full or sparse implementation…
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Circuit-Performance Implications for Double-Gate MOSFET Scaling below 25nm
- …Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It …
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Iterative Decoder Architectures
- …Implementation constraints imposed on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the d…
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PEAK-TO-AVERAGEPOWERRATIOREDUCTION INANFDMBROADCASTSYSTEM
- …ABSTRACT a PAR-reduction solution that can be applied to a general frequency-division multiplexing (FDM) system. Digital predistortion is a technique used to reduce the signal Various methods have been formulated to achievePAR dynamic range in a multichannel system in order to improve reduction in m…
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15-3 A 6-b DAC and Analog DRAM for a Maskless Lithography Interface in 90 nm CMOS
- …Abstract- A parallel, 12µm-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3µm × 3µm analog DRAM cells in a 2.5/1V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charg…
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A 1.2V, 10.8mW, 500kHz Sigma-Delta Modulator with 84dB
- …A 1.2V switched-capacitor sigma-delta modulator achieves 96dB peak SFDR and 84dB peak SNDR at 1MS/s in 2 4…
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Power and Area Efficient VLSI Architectures for Communication Signal Processing
- …Abstract—A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balanc…
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VLSI Architectures for Iterative Decoders in Magnetic Recording Channels
- …VLSI implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response m…
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