Searching for "Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm." – sorted by Relevance.
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Architectural Optimization for a 1.82Gbits/sec VLSI
- Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
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K. Ko, D. Naccache, and C. Paar (Eds.): CHES 2001, LNCS 2162, pp. 51--64, 2001.
- Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
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