Searching for authors named "Anuja Sehgal" – sorted by Relevance.
6 documents found, showing 1 through 6.
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Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
- ….00 (c) 2004 IEEE Anuja Sehgal and Krishnendu Chakrabarty Department of Electrical & Computer Engineering…
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SOC Test Planning Using Virtual Test Access Architectures
- … Virtual Test Access Architectures Anuja Sehgal , Vikram Iyengar and Krishnendu Chakrabarty Department…
- Cited by 4 (4 self) – Add To MetaCart
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Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
- …Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores Anuja Sehgal, Fang Liu, Sule Ozev…
- Cited by 1 (0 self) – Add To MetaCart
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IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
- …IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores Anuja Sehgal ¡ Sandeep Kumar…
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Test infrastructure design for mixed-signal SOCs with wrapped analog cores
- … Test Infrastructure Design for Mixed-Signal SOCs With Wrapped Analog Cores Anuja Sehgal, Student Member…
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Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers
- …44.2 ABSTRACT Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers £ Anuja…
- Cited by 2 (0 self) – Add To MetaCart
Showing 1 through 6.
